
/*
//////////////////////////////////////////////////////////////////////////
//      Copyright 2000 Velocity Communication, Inc.
//      This Velocity proprietary information must be maintained in the
//      strictest of confidence and may not be copied, disclosed, or used
//      without the express written consent of an officer of Velocity
//      Communication, Inc.
//
//      $Revision: 1.1 $
//
//      Author: shrinath
//
//      Description: Base addresses for the bme internal/external memories. 
//


////////////////////////////////////////////////////////////////////////
*/




#define  XFIFO_MEMBASE    0xc0000000    
#define  YFIFO_MEMBASE    0xc1000000    
#define  TFI_MEMBASE      0xc2000000       
#define  ZFIFO_MEMBASE    0xc3000000    
#define  AFIFO_MEMBASE    0xc4000000    
#define  BFIFO_MEMBASE    0xc5000000      
#define  CFIFO_MEMBASE    0xc6000000      
#define  HIC_MEMBASE      0xc7000000      
#define  DMC_MEMBASE      0xc8000000     
#define  TGT_MEMBASE      0xc9000000    
#define  TOT_MEMBASE      0xca000000   
#define  ROT_MEMBASE      0xcb000000  
#define  TEQ_MEMBASE      0xcc000000  
#define  FET_MEMBASE      0xcd000000  
#define  FMC_MEMBASE      0xce000000  
#define  RMC_MEMBASE      0xcf000000       
#define  DMF_MEMBASE      0xd0000000  
#define  BFR_MEMBASE      0xd1000000  
#define  SMC_MEMBASE      0xd2000000  


#define  DPRAM_MEMBASE    0xa0000000   
#define  EMI_MEMBASE      0x40000000       
#define  IRAM_MEMBASE     0x0              


#define  FMC_DCMEMBASE    0xce010000 
#define  RMC_DCMEMBASE    0xcf010000
#define  DMC_DCMEMBASE    0xc8010000 


#define BOOT_BASE   0x80000000   
#define FPGA_ROM2   0x80000200   
#define PBUS_BASE   0x20000000   


#define DATA_SPACE       0x40100000  
#define TOT_OFFSET       0x0  
#define TGT_OFFSET       0x10000  
#define ICACHE_OFFSET    0x20000  

