/**************************************************************
**
** C-SIMULATION, Copyright (C) 2000-2002
** Ikanos Communication, Fremont, CA 
** All rights reserved.
**
** The information and contents of this file are the
** proprietary information of Ikanos Communication and may not
** be disclosed or used without the formal written approval of 
** Ikanos Communication
**
***************************************************************
*/
#include <stdio.h>
#include <string.h>

#include "bme.h"
#include "bme_app.h"
#include "mem.h"
#include "include/afe.h"
#include "include/initASICHardware.h"
#include "include/framercpu.h"
#include "include/sdram_map.h"
#include "include/drvUtils.h"
#include "hostType.h"

int	shadowSNRContextTable[40];
int	shadowDeMapperContextTable[40];
int	shadowMapperContextTable[40];
int	shadowXFIFOFastContextTable[40];
int	shadowXFIFOIntlContextTable[40];
int	shadowYFIFOContextTable[40];
int	shadowZFIFOContextTable[40];
int	shadowAFIFOContextTable[40];
int	shadowBFIFOIntlContextTable[40];
int	shadowBFIFOFastContextTable[40];
int	shadowCFIFO0ContextTable[40];
int	shadowCFIFO1ContextTable[40];

void readContextTables ()
{
	readPIO_Regs ((int *)SNRCTX, 		NUM_DSL_CHANNELS,  shadowSNRContextTable);
	readPIO_Regs ((int *)DMPCTX, 		NUM_DSL_CHANNELS,  shadowDeMapperContextTable);
	readPIO_Regs ((int *)MAP_MCT, 		NUM_DSL_CHANNELS,  shadowMapperContextTable);
	readPIO_Regs ((int *)XFIFOF_CXFT_A, NUM_DSL_CHANNELS,  shadowXFIFOFastContextTable);
	readPIO_Regs ((int *)XFIFOI_CXFT_A, NUM_DSL_CHANNELS,  shadowXFIFOIntlContextTable);
	readPIO_Regs ((int *)YFIFO_CYFT_A,  NUM_DSL_CHANNELS,  shadowYFIFOContextTable);
	readPIO_Regs ((int *)ZFIFO_CZFT_A,  NUM_DSL_CHANNELS,  shadowZFIFOContextTable);
	readPIO_Regs ((int *)CAFT_A, 		NUM_DSL_CHANNELS,  shadowAFIFOContextTable);
	readPIO_Regs ((int *)CBFT_A, 		NUM_DSL_CHANNELS,  shadowBFIFOFastContextTable);
	readPIO_Regs ((int *)CBIT_A, 		NUM_DSL_CHANNELS,  shadowBFIFOIntlContextTable);
	readPIO_Regs ((int *)CCFT0_A, 		NUM_DSL_CHANNELS,  shadowCFIFO0ContextTable);
	readPIO_Regs ((int *)CCFT1_A, 		NUM_DSL_CHANNELS,  shadowCFIFO1ContextTable);
}

void enable_tni0()
{
	// TNI Programming
	// Utopia level 2, tx ch1 -> Tx Phy port 0
    writePIO_SingleRegChannel((int *)0xe0000700, 0, 0x00000000);
    // writePIO_SingleRegChannel( 0xe0000000, 0, 0x80000000);
    writePIO_SingleRegChannel( (int *)0xe0000000, 0, 0x80000000);
    writePIO_SingleRegChannel((int *) 0xe0000200, 0, 0x80000000);
    writePIO_SingleRegChannel((int *) 0xe0000400, 0, 0x80000000);
	// End of Utopia setting
    writePIO_SingleRegChannel((int *) 0xe0040100, 0, 0x0);
}



/*
************************************************************************
	Function: initASICHardware
	
	Description: Init all the asics and read back the contexttables. 
		
	Return Value: 
************************************************************************
*/

void init_XFIFO(int tot_num_ports)
{
	int 	i;
	int		ff_size = 16384/(128*tot_num_ports);
	
	for(i=0;i<tot_num_ports;i++) {
		// fast  bankA & B  ch-num
		writePIO_SingleRegChannel((int *)(XFIFOF_CXFT_B), i, 0x0);
		// 0x29 = 0010 1001
		// 	Valid = 1
		//	FF_SRC = ATM
		//	FF_DEST = FRM Acc
		//	FF_SIZE = 4K
		//	START_ADDR = 0x0

		writePIO_SingleRegChannel((int *)(XFIFOF_CXFT_A), i, 0x29+((i*ff_size)<<6));
		// slow  bankA & B  ch-num
		writePIO_SingleRegChannel((int *)(XFIFOI_CXFT_B), i, 0x0);
		// 0x29 = 0010 1001
		// 	Valid = 1
		//	FF_SRC = ATM
		//	FF_DEST = FRM Acc
		//	FF_SIZE = 4K
		//	START_ADDR = 0x0
		writePIO_SingleRegChannel((int *)(XFIFOI_CXFT_A), i, 0x29+((ff_size*i)<<6));
	}		
}

void init_YFIFO(int tot_num_ports) 
{
	int		i;
		
	writePIO_SingleRegChannel((int *)YFIFO_TOFT, 0, 0x1);   // initialize the tone order fifo
	for(i=0;i<tot_num_ports;i++) {
		writePIO_SingleRegChannel((int *)YFIFO_CYFT_A, i, 0x49+((65536*i/128)<<7));
		writePIO_SingleRegChannel((int *)YFIFO_CYFT_B, i, 0x0);
		writePIO_SingleRegChannel((int *)YFIFO_CYFT_C, i, 0x1<<24);		// depth of 1 byte
		writePIO_SingleRegChannel((int *)YFIFO_CYFT_D, i, 0x0);
	}
}

void init_Mapper(int tot_num_ports, int trellis_enable, int ifft_scale, int tot_tones)
{
	int i;
	
	for(i=0;i<tot_num_ports;i++) {
		writePIO_SingleRegChannel((int *)(MAP_MCT), i, (4096/128)*0 + (tot_tones<<8) + (ifft_scale<<11) + (trellis_enable<<15));
	}
}

void init_ZFIFO(int tot_num_ports)
{
	int 	i;
	int		ff_size = 32*1024;
	int		size_code = 0x8;	
	
	for(i=0; i<tot_num_ports; i++) {
	 	writePIO_SingleRegChannel((int *) (ZFIFO_CZFT_A), i, ((ff_size*i/128)<<7) + (size_code<<3) + 1);		 // 32 k per channel
		writePIO_SingleRegChannel((int *) (ZFIFO_CZFT_C), i, 0);
		writePIO_SingleRegChannel((int *) (ZFIFO_CZFT_D), i, 0);	
	}
}

void set_ZFIFO_wrt_ptr(int wrt_pos, int ch_num)
{
	writePIO_SingleRegChannel((int *) (ZFIFO_CZFT_D), ch_num, wrt_pos);
}


void init_VBUS_no_ce(int ce_on)
{
  
    int cst_dword;

    if (ce_on) {
	  cst_dword = 0x45;
	} else {
	  cst_dword = 0x40;
	}
	
    //For 4-slot; CST = 32; tx-size = 0x40; interval = 0x70
	//interval = 0x70
	writePIO_SingleRegChannel((int*)VIF_ICCR, 0, ((0x70 << 16) + 0x70));
	//writePIO_SingleRegChannel((int*)VIF_ICCR, 0, ((0x96 << 16) + 0x96));
	//For 4-slot; CST = 32
	writePIO_SingleRegChannel((int*)VIF_SCCR,  0, ((0x1f << 24) + (0x1f << 16) + (0x03 << 8) + 0x3));

	writePIO_SingleRegChannel((int*)VIF_CST0L, 0, ((0x0 << 8) + 0x00));

	writePIO_SingleRegChannel((int*)VIF_CST1L, 0, ((0x0 << 8) + 0x00));

	writePIO_SingleRegChannel((int*)VIF_CST2L, 0, ((0x0 << 8) + 0x00));

	writePIO_SingleRegChannel((int*)VIF_CST3L, 0, ((0x0 << 8) + 0x00));

	writePIO_SingleRegChannel((int*)VIF_CST4L, 0, ((0x0 << 8) + 0x00));

	writePIO_SingleRegChannel((int*)VIF_CST5L, 0, ((0x0 << 8) + 0x00));

	writePIO_SingleRegChannel((int*)VIF_CST6L, 0, ((0x0 << 8) + 0x00));

	writePIO_SingleRegChannel((int*)VIF_CST7L, 0, ((0x0 << 8) + 0x00));


	writePIO_SingleRegChannel((int*)VIF_CST8L, 0, ((0x0 << 8) + 0x01));

	writePIO_SingleRegChannel((int*)VIF_CST9L, 0, ((0x0 << 8) + 0x01));

	writePIO_SingleRegChannel((int*)VIF_CST10L, 0, ((0x0 << 8) + 0x01));

	writePIO_SingleRegChannel((int*)VIF_CST11L, 0, ((0x0 << 8) + 0x01));

	writePIO_SingleRegChannel((int*)VIF_CST12L, 0, ((0x0 << 8) + 0x01));

	writePIO_SingleRegChannel((int*)VIF_CST13L, 0, ((0x0 << 8) + 0x01));

	writePIO_SingleRegChannel((int*)VIF_CST14L, 0, ((0x0 << 8) + 0x01));

	writePIO_SingleRegChannel((int*)VIF_CST15L, 0, ((0x0 << 8) + 0x01));


	writePIO_SingleRegChannel((int*)VIF_CST16L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST17L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST18L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST19L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST20L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST21L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST22L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST23L, 0, ((0x1 << 8) + 0x08));
	

	writePIO_SingleRegChannel((int*)VIF_CST24L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST25L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST26L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST27L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST28L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST29L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST30L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST31L, 0, ((0x1 << 8) + 0x09));


	writePIO_SingleRegChannel((int*)VIF_CST0H, 0, ((cst_dword << 16) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST1H, 0, ((cst_dword << 16) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST2H, 0, ((cst_dword << 16) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST3H, 0, ((cst_dword << 16) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST4H, 0, ((cst_dword << 16) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST5H, 0, ((cst_dword << 16) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST6H, 0, ((cst_dword << 16) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST7H, 0, ((cst_dword << 16) + cst_dword));



	writePIO_SingleRegChannel((int*)VIF_CST8H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST9H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST10H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST11H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST12H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST13H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST14H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST15H, 0, ((cst_dword << 24) + (0x40 << 16) + (cst_dword << 8) + 0x40));



	writePIO_SingleRegChannel((int*)VIF_CST16H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST17H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST18H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST19H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST20H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST21H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST22H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST23H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST24H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST25H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST26H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST27H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST28H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST29H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST30H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST31H, 0, ((0x40 << 16) + 0x40));


	writePIO_SingleRegChannel((int*)VIF_BCR, 0, 0x80000000);
}


void init_VBUS(int ce_on, int vbus_chan_num, int afe_num, int afe_chan)
{

	int cst_dword;
	int interval;

    if (ce_on) {
		cst_dword = 0x45;
	} else {
	  	cst_dword = 0x40;
	}
	
    //For 4-slot; CST = 32; tx-size = 0x40; interval = 0x70
	interval = 0x65;
	writePIO_SingleRegChannel((int*)VIF_ICCR, 0, ((interval << 16) + interval));
	
	writePIO_SingleRegChannel((int*)VIF_SCCR,  0, ((0x1f << 24) + (0x1f << 16) + (0x03 << 8) + 0x3));

	if (afe_chan == 2) {
		writePIO_SingleRegChannel((int*)VIF_CST0L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST1L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST2L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST3L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST4L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST5L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST6L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST7L, 0, ((0x0 << 8) + 0x00));


		writePIO_SingleRegChannel((int*)VIF_CST8L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST9L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST10L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST11L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST12L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST13L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST14L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST15L, 0, ((0x0 << 8) + 0x01));
	} else if (afe_chan == 1) {

		writePIO_SingleRegChannel((int*)VIF_CST0L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST1L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST2L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST3L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST4L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST5L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST6L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST7L, 0, ((0x0 << 8) + 0x01));

		writePIO_SingleRegChannel((int*)VIF_CST8L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST9L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST10L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST11L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST12L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST13L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST14L, 0, ((0x0 << 8) + 0x00));

		writePIO_SingleRegChannel((int*)VIF_CST15L, 0, ((0x0 << 8) + 0x00));
	}

	writePIO_SingleRegChannel((int*)VIF_CST16L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST17L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST18L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST19L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST20L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST21L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST22L, 0, ((0x1 << 8) + 0x08));

	writePIO_SingleRegChannel((int*)VIF_CST23L, 0, ((0x1 << 8) + 0x08));
	

	writePIO_SingleRegChannel((int*)VIF_CST24L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST25L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST26L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST27L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST28L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST29L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST30L, 0, ((0x1 << 8) + 0x09));

	writePIO_SingleRegChannel((int*)VIF_CST31L, 0, ((0x1 << 8) + 0x09));


	writePIO_SingleRegChannel((int*)VIF_CST0H, 0, 0);

	writePIO_SingleRegChannel((int*)VIF_CST1H, 0, 0);

	writePIO_SingleRegChannel((int*)VIF_CST2H, 0, 0);

	writePIO_SingleRegChannel((int*)VIF_CST3H, 0, 0);

	writePIO_SingleRegChannel((int*)VIF_CST4H, 0, 0);

	writePIO_SingleRegChannel((int*)VIF_CST5H, 0, 0);

	writePIO_SingleRegChannel((int*)VIF_CST6H, 0, 0);

	writePIO_SingleRegChannel((int*)VIF_CST7H, 0, 0);



	writePIO_SingleRegChannel((int*)VIF_CST8H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST9H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST10H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST11H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST12H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST13H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST14H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));

	writePIO_SingleRegChannel((int*)VIF_CST15H, 0, ((cst_dword << 24) + (cst_dword << 16) + (cst_dword << 8) + cst_dword));



	writePIO_SingleRegChannel((int*)VIF_CST16H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST17H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST18H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST19H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST20H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST21H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST22H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST23H, 0, ((0x40 << 16) + 0x40));
	
	

	writePIO_SingleRegChannel((int*)VIF_CST24H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST25H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST26H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST27H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST28H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST29H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST30H, 0, ((0x40 << 16) + 0x40));

	writePIO_SingleRegChannel((int*)VIF_CST31H, 0, ((0x40 << 16) + 0x40));


	writePIO_SingleRegChannel((int*)VIF_BCR, 0, 0x80000000);
}

void init_vbus_all_chan_4k(int ce_enable)
{
	int tmp;
	int val;
	
	if(ce_enable)	{
		writePIO_SingleRegChannel((int*)VIF_ICCR, 0, 0x00750075);	
		val =0x26262222;
	}
	else {
		writePIO_SingleRegChannel((int*)VIF_ICCR, 0, 0x00590059);	
		val = 0x20202020;	
		
	}

// 	writePIO_SingleRegChannel((int*)VIF_SCCR,  0, 0x0f0f0707);
    writePIO_SingleRegChannel((int*)VIF_SCCR,  0, 0x0f0f0707);
	writePIO_SingleRegChannel((int*)VIF_CST0L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST0H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST1L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST1H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST2L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST2H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST3L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST3H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST4L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST4H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST5L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST5H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST6L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST6H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST7L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST7H, 0, val);
	
	writePIO_SingleRegChannel((int*)VIF_CST8L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST8H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST9L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST9H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST10L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST10H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST11L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST11H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST12L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST12H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST13L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST13H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST14L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST14H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST15L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST15H, 0, val);

	tmp = 0x204; // 0x102 orig   0x204 for AFE2 channel 4 of eight ports configration
	writePIO_SingleRegChannel((int*)VIF_CST16L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST16H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST17L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST17H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST18L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST18H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST19L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST19H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST20L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST20H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST21L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST21H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST22L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST22H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST23L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST23H,0, val);

	tmp = 0x205; // 0x103 orig   0x205 for AFE2 channel 5 of eight ports configration
	writePIO_SingleRegChannel((int*)VIF_CST24L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST24H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST25L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST25H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST26L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST26H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST27L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST27H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST28L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST28H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST29L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST29H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST30L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST30H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST31L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST31H,0, val);
                                                                                                                                                                                                                                   
	writePIO_SingleRegChannel((int*)VIF_BCR,0, 0xc0000000);

}

void init_vbus_all_chan_1k(int ce_enable)
{
	int tmp;
	int val;
	
	if(ce_enable)	{
		writePIO_SingleRegChannel((int*)VIF_ICCR, 0, 0x00610061);	
		val =0x26262222;
	}
	else {
		writePIO_SingleRegChannel((int*)VIF_ICCR, 0, 0x00590059);	
		val = 0x20202020;			
	}
	
	writePIO_SingleRegChannel((int*)VIF_SCCR,  0, 0x0f0f0707);
	
	writePIO_SingleRegChannel((int*)VIF_CST0L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST0H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST1L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST1H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST2L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST2H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST3L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST3H, 0, val);
	
	writePIO_SingleRegChannel((int*)VIF_CST4L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST4H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST5L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST5H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST6L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST6H, 0, val);
	writePIO_SingleRegChannel((int*)VIF_CST7L, 0, 0x00000001);
	writePIO_SingleRegChannel((int*)VIF_CST7H, 0, val);
	
	tmp = 0x102;
	writePIO_SingleRegChannel((int*)VIF_CST16L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST16H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST17L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST17H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST18L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST18H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST19L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST19H,0, val);
	
	tmp = 0x103;
	writePIO_SingleRegChannel((int*)VIF_CST20L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST20H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST21L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST21H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST22L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST22H,0, val);
	writePIO_SingleRegChannel((int*)VIF_CST23L,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST23H,0, val);
	writePIO_SingleRegChannel((int*)VIF_BCR,0, 0xc0000000);
}

void init_vbus_all_chan_8k(int ce_enable)
{
	int	tmp;

	logMsg("\n init vbus for 8k");
	writePIO_SingleRegChannel((int*)VIF_ICCR,  0, 0x00750075);
	writePIO_SingleRegChannel((int*)VIF_SCCR,  0, 0x0f0f0707);
	
	writePIO_SingleRegChannel((int*)VIF_CST0L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST0H, 0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST1L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST1H, 0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST2L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST2H, 0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST3L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST3H, 0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST4L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST4H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST5L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST5H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST6L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST6H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST7L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST7H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST8L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST8H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST9L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST9H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST10L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST10H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST11L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST11H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST12L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST12H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST13L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST13H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST14L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST14H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST15L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST15H ,0, 0x26262222);
	
	tmp = 0x102;
	writePIO_SingleRegChannel((int*)VIF_CST16L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST16H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST17L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST17H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST18L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST18H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST19L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST19H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST20L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST20H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST21L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST21H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST22L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST22H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST23L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST23H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST24L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST24H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST25L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST25H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST26L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST26H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST27L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST27H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST28L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST28H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST29L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST29H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST30L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST30H ,0, 0x26262222);
	writePIO_SingleRegChannel((int*)VIF_CST31L ,0, tmp);
	writePIO_SingleRegChannel((int*)VIF_CST31H, 0, 0x26262222);
	
	writePIO_SingleRegChannel((int*)VIF_BCR,   0, 0xc0000000);
}

void init_vbus_all_chan_8k_640ce(int ce_enable)
{
	logMsg("\n init vbus for 8k");
	writePIO_SingleRegChannel((int*)VIF_ICCR,  0, 0x007d007d);
	writePIO_SingleRegChannel((int*)VIF_SCCR,  0, 0x0f0f0707);
	
	writePIO_SingleRegChannel((int*)VIF_CST0L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST0H, 0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST1L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST1H, 0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST2L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST2H, 0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST3L, 0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST3H, 0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST4L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST4H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST5L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST5H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST6L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST6H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST7L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST7H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST8L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST8H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST9L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST9H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST10L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST10H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST11L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST11H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST12L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST12H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST13L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST13H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST14L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST14H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST15L ,0, 0x00000000);
	writePIO_SingleRegChannel((int*)VIF_CST15H ,0, 0x25252525);
	
	writePIO_SingleRegChannel((int*)VIF_CST16L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST16H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST17L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST17H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST18L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST18H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST19L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST19H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST20L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST20H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST21L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST21H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST22L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST22H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST23L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST23H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST24L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST24H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST25L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST25H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST26L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST26H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST27L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST27H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST28L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST28H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST29L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST29H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST30L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST30H ,0, 0x25252525);
	writePIO_SingleRegChannel((int*)VIF_CST31L ,0, 0x00000108);
	writePIO_SingleRegChannel((int*)VIF_CST31H, 0, 0x25252525);
	
	writePIO_SingleRegChannel((int*)VIF_BCR,   0, 0xc0000000);
}

 

void init_AFIFO(int tot_num_ports, int ff_src, int ff_dst)
{
	int 	i;
	int 	ff_size = 32768;
	int		ff_code = 0x8;	
	
	for(i=0; i<tot_num_ports; i++) {
		writePIO_SingleRegChannel((int *)(CAFT_A), i, 1 + (ff_src<<1) + (ff_dst<<2) + (ff_code<<3) + ((i*ff_size/128)<<7));  // enable fifo, FF_SRC = v_bus, FF_DST = DMT, FF_SIZE = 8
		writePIO_SingleRegChannel((int *)(CAFT_C), i, 0x0);
		writePIO_SingleRegChannel((int *)(CAFT_D), i, 0x0);	
	}
}


void set_AFIFO_rd_ptr(int rd_pos, int ch_num)
{
	writePIO_SingleRegChannel((int *) (CAFT_C), ch_num, rd_pos);
}

void init_DeMapper(int tot_num_ports)
{
	int		i;
	
	for(i=0;i<tot_num_ports;i++) {
		writePIO_SingleRegChannel((int *)(DMPCTX), i, (6<<28)+(2048<<16)+((2048*4*i/256)<<8)+(2048*2*i/128));
	}
}

void set_loop_gain(int gain, int channel)
{
	writePIO_SingleRegChannel((int *)(MDPMUT), channel, gain&0xf);
}

void init_SNR(int num_channels, int toneTblNum, int losEnable, int TnDetectEnb, int SNRenb)
{
	int i;
	
	for(i=0;i<num_channels;i++)	
		writePIO_SingleRegChannel((int *)SNRCTX, i, 0x0 + (SNRenb<<7) + (TnDetectEnb<<8) + (losEnable<<9) + (toneTblNum<<10));
}

void init_BFIFO(int num_channels, int ff_src, int ff_dst)
{
	int i;
	
	for(i=0;i<num_channels;i++) {
		writePIO_SingleRegChannel((int *)CDMT, 	i, 0x1); // valid =1, FF_SRC = 0(demapper), FF_DST = 0(BFIFO)
		writePIO_SingleRegChannel((int *)CBFT_A,i, 1+(4<<3)+((i*2048/128)<<6));
		writePIO_SingleRegChannel((int *)CBFT_B, i, 0x0);
		writePIO_SingleRegChannel((int *)CBIT_A, i, 1+(ff_src<<1) + (ff_dst<<2) + (8<<3)+((i*32768/128)<<7));
		writePIO_SingleRegChannel((int *)CBIT_B, i, 0x0);
		writePIO_SingleRegChannel((int *)CBIT_C, i, 0x0);
		writePIO_SingleRegChannel((int *)CBIT_D, i, 0x0);
	}	
}

void init_CFIFO(int num_channels)
{
   	int i;
	
	for(i=0;i<num_channels;i+=2) {
		writePIO_SingleRegChannel((int *)CCFT0_A, i, 1+(5<<3)+((4096*i/128)<<6));
		writePIO_SingleRegChannel((int *)CCFT0_B, i, 0x0);				
		writePIO_SingleRegChannel((int *)CCFT1_A, i+1, 1+(5<<3)+((4096*(i+1)/128)<<6));					
		writePIO_SingleRegChannel((int *)CCFT1_B, i+1, 0x0);	
	}
}



void enable_rni()
{
	// Programming RNI
	writePIO_SingleRegChannel((int *)0xe0028000, 0, 0x00350000);
	// Enable RNI Phy port 0
	writePIO_SingleRegChannel((int *)0xe0028100, 0, 0x80000000);
	// End of RNI setting
}




void init_SBit()
{
	int	i;
	
	u16 FEQrmsCoarseShift[16] = { 
		7-1, 6-1, 6-1, 5-1, 5-1, 4-1, 4-1, 3-1, 
		3-1, 2-1, 2-1, 1-1, 1-1, 0, 0, 0
	};
	
	for(i=0;i<16;i++)
		writePIO_SingleRegChannel((int *)DMPSBT+i, 0,  FEQrmsCoarseShift[i]&0xf);
}

void init_mapper_PTONE(u16 prd_mask, u16 ptone_index)
{

	writePIO_SingleRegChannel((int *)PTONE_2048T, 0, (prd_mask<<16)|ptone_index);
}

void init_demapper_PTONE(u16 prd_mask, u16 ptone_index)
{
 	writePIO_SingleRegChannel((int *)DMPPLT, 0, (prd_mask<<16)|ptone_index);

	writePIO_SingleRegChannel((int *)(DMPPLT+0x18), 0, (prd_mask<<16)|ptone_index);
}

void set_feq_mu(u8 chan_num, u8 mu)
{
	writePIO_SingleRegChannel((int *)MDPMUT, chan_num, mu&0xf);
}

void enable_fmc()
{
	writePIO_SingleRegChannel((int *)FCPU_FMC_FCR, 0x0, 0x1);
}

void enable_rmc()
{
	writePIO_SingleRegChannel((int *)RMC_RCR, 0x0, 0x1);
}

void enable_dmc()
{
	writePIO_SingleRegChannel((int *)DMC_DCR, 0x0, 0x1);
}

void enable_vbus(int vbus_num)
{
	int	data;
	
	if(vbus_num!=0 && vbus_num!=1)
		printf("\n invalid vbus number");
		
	data = 1<<(31-vbus_num);
	writePIO_SingleRegChannel((int *) VIF_BCR, 0, data);
}

void disable_vbus()
{
	writePIO_SingleRegChannel((int *) VIF_BCR, 0, 0x0);
}

void initASICHardware ()
{

	memset((u8 *)shadowSNRContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowDeMapperContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowMapperContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowXFIFOFastContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowXFIFOIntlContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowYFIFOContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowZFIFOContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowAFIFOContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowBFIFOIntlContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowBFIFOFastContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowCFIFO0ContextTable, 0x0, 40*sizeof(int));
	memset((u8 *)shadowCFIFO1ContextTable, 0x0, 40*sizeof(int));

	// TX initialization
	init_XFIFO(NUM_DSL_CHANNELS);
	init_YFIFO(NUM_DSL_CHANNELS);
	init_mapper_PTONE(0x00A0, 4095);
	init_Mapper(NUM_DSL_CHANNELS, 0, 9, 6); // disable trellis, fft scale 9, and tot tones = 2048
	init_ZFIFO(NUM_DSL_CHANNELS);
	// RX initialization
    init_AFIFO(NUM_DSL_CHANNELS, 0, 0);
	init_DeMapper(NUM_DSL_CHANNELS);
	init_demapper_PTONE(0x00A0, 4095);
	init_SNR(NUM_DSL_CHANNELS, 1, 1, 1,1);
	init_SBit();
	init_BFIFO(NUM_DSL_CHANNELS, 0, 1);
	init_CFIFO(NUM_DSL_CHANNELS);
	initCpuCmdQ();		
	readContextTables ();	
	initAFE (1);
}

void set_ifft_scale_shift(int chan_num, int ifft_scale)
{
	int		val;
	int		data;
	
	if(ifft_scale>9) {
		printf("\n %d is not allowed as an ifft scale shift value", ifft_scale);
		return;
	}
	
	val = readPIO_SingleRegChannel((int *)(MAP_MCT), chan_num);
	data = (val&0xffff8000)+((val&0xf)<<11)+(val&0x000003ff);
	writePIO_SingleRegChannel((int *)(MAP_MCT), chan_num, data);
}














