#ifdef CO_30_DIAGS

/*********************************************************/
/*                  INCLUDE FILES                        */
/*********************************************************/
#include <stdio.h>
#include <vxWorks.h>
#include <diags_defines.h>

							  
/*********************************************************/
/*                  LOCAL MACROS                         */
/*********************************************************/
#undef DEBUG_INPUT


/* bit definition */
#define BIT(n)			(1 << n)

#define BIT0			(BIT(0))
#define BIT1			(BIT(1))
#define BIT2			(BIT(2))
#define BIT3			(BIT(3))
#define BIT4			(BIT(4))
#define BIT5			(BIT(5))
#define BIT6			(BIT(6))
#define BIT7			(BIT(7))
#define BIT8			(BIT(8))
#define BIT9			(BIT(9))
#define BIT10			(BIT(10))
#define BIT11   		(BIT(11))
#define BIT12			(BIT(12))
#define BIT13   		(BIT(13))
#define BIT14   		(BIT(14))
#define BIT15			(BIT(15))
#define BIT16   		(BIT(16))
#define BIT17			(BIT(17))
#define BIT18   		(BIT(18))
#define BIT19			(BIT(19))
#define BIT20			(BIT(20))
#define BIT21   		(BIT(21))
#define BIT22			(BIT(22))
#define BIT23   		(BIT(23))
#define BIT24   		(BIT(24))
#define BIT25   		(BIT(25))
#define BIT26   		(BIT(26))
#define BIT27   		(BIT(27))
#define BIT28   		(BIT(28))
#define BIT29   		(BIT(29))
#define BIT30   		(BIT(30))
#define BIT31   		(BIT(31))


#ifdef CPE_50
#define NUM_PORTS_PER_AFE		(1)
#define MAX_PORT_PER_BME        (1)
#else
#define NUM_PORTS_PER_AFE		(4)
#define MAX_PORT_PER_BME        (8)
#endif

//#define AFE_CO30_PATTERN_FILE  "/tgtsvr/"  

#define PIO_AFE_RDWR_CMD		(0xE0018000)
#define PIO_AFE_READ_DATA		(0xE0018004)
#define PIO_AFE_WRITE_DATA	    (0xE0018008)
#define PIO_AFE_RDWR_STAT		(0xE001800C)

#define AFE_RD_REG				(1 << 31)
#define AFE_WR_REG				(1 << 30)
#define AFE_CMD_PASS			(1 << 2)
#define AFE_CMD_FAIL			(1 << 1)
#define AFE_CMD_BUSY			(1 << 0)


#define MIN_DAC_RANGE			(0)
#define MAX_DAC_RANGE			(16384-1)

#define PORTS_PER_QUAD              4
#define QUAD_BIT_POSITION           (28-2)
#define NUM_OF_QUADS                2
#define PORTS_PER_QUAD_MASK         (PORTS_PER_QUAD-1)

/* Determine if the 28th Quad bit should be set or not (2 bits port number) */
#define MAP_CHAN_TO_QUAD(p)         (u32)(((p) & PORTS_PER_QUAD) << QUAD_BIT_POSITION)

/* Map a channel number into a number local to a quad */
#define MAP_CHAN(p)                 ((p) & PORTS_PER_QUAD_MASK)

/* Find out which Quad (0 or 1) we are dealing with. */
#define QUAD_NUM(p)                 (((p) & PORTS_PER_QUAD) >> 2)

/********************   AFE_CO30 Internal Registers      ************/
#define AFE_VERSION				(0x00)		// GLOBAL Reg

#define AFE_IFE_TYPE			(0x01)		// GLOBAL Reg
	#define AFE_IFE_TYPE_MASK		(BIT0)
	#define UNKNOWN_IFE				(0xFF)
	#define IFE2_TYPE				(0x00)
    #define IFE_CO30_TYPE           (0x01)
    #define IFE_CO50_TYPE           (0x01)

#define AFE_IFE_RETUNE_CTRL	    (0x02)		// GLOBAL Reg
	#define IFE_RETUNE_OFF			(0)
	#define IFE_RETUNE_ON			(1)
	#define SEL_IFE0				(BIT8)
	#define SEL_IFE1				(BIT9)
	#define SEL_IFE2				(BIT10)
	#define SEL_IFE3				(BIT11)
	#define SEL_IFES_MASK			(SEL_IFE0+SEL_IFE1+SEL_IFE2+SEL_IFE3)
	
#define AFE_BAND_GAP_CTRL	    (0x03)		// PER ch
	#define BG_CTL_MASK				(BIT0+BIT1+BIT2+BIT3)
	
#define AFE_PLL_TEST			(0x04)		// PER Ch
	#define PLL_OUT					(BIT9)

//IFE_CPE5	
#define AFE_ADC_DAC_MODE            (0x04)      // PER Ch  //TL: CO5
    #define DAC_MODE                (BIT0)
    #define ADC_MODE                (BIT1)


	

#define AFE_PWR_DOWN			(0x05)		// PER Ch
	#define VTX_PD					(BIT15)		// analog domain
	#define VRX_PD					(BIT14)		// analog domain
	#define RCH_PD					(BIT1)		// digital domain
	#define TCH_PD					(BIT0)		// digital domain
	#define AFE_TX_RX_PD			(VTX_PD+VRX_PD+RCH_PD+TCH_PD)
	#define AFE_TX_RX_PU			(0)

//CO3
#define AFE_ADC_STAT			(0x06)		// PER Ch
	#define ADC_UNDER_FLOW			(BIT1)
	#define ADC_OVER_FLOW			(BIT0)
	
#define AFE_VCXO_CTRL               (0x06)       //CO5
    #define VCXO_CTL1               (0xFFFF0000) //more detailed mapping
    #define VCXO_CTL0               (0x0000FFFF)

	
	
#define AFE_ADC_COEF			(0x07)		// PER Ch
	#define ADC_COEF_MASK			(0x7FFFF)
	
#define AFE_DAC_COEF			(0x08)		// PER Ch
	#define DAC_COEF_MASK			(0xFF)
	
#define AFE_ADC_BIAS			(0x09)		// PER Ch
	#define ADC_BIAS				(BIT0+BIT1+BIT2)
	
#define AFE_DAC_BIAS			(0x0A)		// PER Ch
	#define DAC_BIAS				(BIT0+BIT1+BIT2)

#define AFE_VCXO_CNTRL_2            (0x0B)
    #define VNS_IP_DATA             (0x00003FFF)
    #define VNS_MODEL_SEL           (BIT14)
    #define DITHER_IP               (0x3FFF0000)
    #define DITHER_EN               (BIT30)
    #define VXCO_PD                 (BIT31)


#define AFE_CAL_ADC_CMD			(0x0C)		// PER Ch
	#define CRQ_VADC				(BIT0)
	
#define AFE_CAL_DAC_CMD			(0x0D)		// PER Ch
	#define CRQ_VDAC				(BIT0)
	
#define AFE_CAL_ADC_STAT		(0x0E)		// PER Ch
	#define VADC_RDY_A 	 			(BIT4)
	#define VADC_RDY_B 	 			(BIT20)
	#define VADC_RDY 	 			(BIT4)
	
	
#define AFE_CAL_DAC_STAT		(0x0F)		// PER Ch
	#define VDAC_RDY				(BIT4)
	
#define AFE_ADC_DAC_TEST		(0x10)		// PER Ch
	#define TEST_ADC_B				(BIT2)
	#define TEST_ADC_A				(BIT1)
	#define TEST_DAC				(BIT0)
	#define TEST_ADC				(BIT1)
	
#define AFE_ANALOG_TEST			(0x11)		// GLOBAL Reg
	#define ANALOG_TEST_MODE_MASK	(0xFFFF)
	
#define AFE_MISC				(0x12)		// PER Ch
	#define ANALOG_TEST_MODE_MASK	(0xFFFF)
	
#define AFE_RESERVED2			(0x13)
#define AFE_DIGITAL_TEST		(0x14)		// PER Ch
	#define LOOPBACK_EN				(BIT0)		// digital loopback
	
#define AFE_IFE_RDWR_CMD		(0x15)		// GLOBAL Reg
	#define IFE_REG_RD				(BIT31)
	#define IFE_REG_WR				(BIT30)
	#define IFE_NUM					(BIT8+BIT9)
	#define IFE_REG_ADDR			(BIT0+BIT1+BIT2+BIT3+BIT4)
	
#define AFE_IFE_REG_RD_DATA	    (0x16)		// GLOBAL Reg

#define AFE_IFE_REG_WR_DATA	    (0x17)		// GLOBAL Reg

#define AFE_IFE_RDWR_STAT		(0x18)		// GLOBAL Reg
	#define IFE_CMD_PASS			(BIT2)
	#define IFE_CMD_FAIL			(BIT1)
	#define IFE_CMD_BUSY			(BIT0)
	#define IFE_STATUS_CLEAR		(IFE_CMD_PASS + IFE_CMD_FAIL)
#define AFE_HLD_REG_RD_WR_STAT      (0x1A)      // GLOBAL Reg
    #define HLD_STAT                (BIT31)
    #define WR_DATA                 (0x0FFF0000) //27:16
    #define RD_DATA                 (0x00000FFF) //11:0
#define AFE_HLD_RDWR_CMD            (0x19)      // GLOBAL Reg
    #define HLD_REG_RD              (BIT31)
    #define HLD_REG_WR              (BIT30)
    #define HLD_NUM                 (BIT0)

#define AFE_HLD_RDWR_STAT      (0x1A)      // GLOBAL Reg
    #define HLD_STAT                (BIT31)
    #define WR_DATA                 (0x0FFF0000) //27:16
    #define RD_DATA                 (0x00000FFF) //11:0



#define AFE_ADC_B_OFFSET                (0x1B)
    #define USE_ADC_B_DATA              (BIT29)
    #define HW_OFFSET_CAL_START         (BIT28)
    #define HW_OFFSET_CAL_EN            (BIT27)
    #define ADC_B_CORRECTION_OFFSET_A   (0x07FFC000) //(26:14)
    #define ADC_B_CORRECTION_OFFSET_B   (0x00003FFE) //(13:1)
    #define ADC_B_CORRECTION_BYPASS     (BIT0)

#define AFE_ADC_B_GAIN                  (0x1C)
    #define ADC_B_CORRECTION_GAIN       (0x00001FFF) //(12:0)

#define AFE_GPIO_RD_WD_DATA             (0x1D)
    #define GPIO_WR_DATA                (0x0000FF00) //15:8    
    #define GPIO_RD_DATA                (0x000000FF) //7:0

#define AFE_ADC_K1_K2                   (0x1E)
    #define ADC_K2                      (0x1FFF0000) //28:16
    #define ADC_K1                      (0x00001FFF) //12:0

#define AFE_ADC_K3_K4                   (0x1F)
    #define ADC_K4                      (0x1FFF0000) //28:16
    #define ADC_K3                      (0x00001FFF) //12:0


/********************   IFE2 Internal Registers   *******************/
#define IFE2_REG_MASK			(BIT0)

#define IFE2_REG_0				(0x00)
	#define IFE2_PGA2_MASK			(BIT30+BIT29)
	#define IFE2_PGA1_MASK			(BIT28+BIT27+BIT26+BIT25+BIT24)
	#define IFE2_VGA_MASK			(BIT19+BIT18+BIT17+BIT16)
	#define IFE2_FC_TXLPF			(BIT15)
	#define IFE2_TXLPF_MASK			(BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	#define IFE2_FC_RXLPF			(BIT7)
	#define IFE2_RXLPF_MASK			(BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)

#define IFE2_REG_1				(0x01)
	#define IFE2_RXHPF_MASK			(BIT30+BIT29+BIT28+BIT27+BIT26+BIT25+BIT24)
	#define IFE2_REG_PD				(BIT23)
	#define IFE2_LNA_MASK			(BIT22+BIT21)
	#define IFE2_HPFO_MASK			(BIT18)
	#define IFE2_HPF_MASK			(BIT17+BIT16)
		#define HPF_FC_375M				(0)
		#define HPF_FC_18M				(1)
		#define HPF_INTERNAL_BYPASS		(2)
		#define HPF_EXTERNAL_BYPASS		(3)
	#define IFE2_REVID_MASK			(BIT15+BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	
	
	
#define IFE_CO5_REV_ID				(0)
	#define	IFE_REV_ID_MASK			(0xffff)
#define IFE_CO5_TUNER				(8)
	#define IFE_CO5_TUNER_REG_MISC	(0xff)
#define IFE_CO5_BANDGAP				(0X10)
	#define IFE_CO5_BANDGAP_CTL		(BIT4 | BIT3 | BIT2 | BIT1)
	#define IFE_CO5_BANDGAP_PD		(BIT0)
#define IFE_CO5_COM_MISC			(0X18)
#define IFE_CO5_TXLPF				(1)
	#define IFE_CO5_TXLPF_MISC	    (BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25+BIT24+BIT23+BIT22+BIT21)
	#define IFE_CO5_TXLPF_FC9MS	    (BIT20)
	#define IFE_CO5_TXLPF_PD	    (BIT19)
	#define IFE_CO5_TXLPF_CURR_CTL  (BIT18+BIT17+BIT16)
	#define IFE_CO5_TXLPF_SEC2		(BIT15+BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	#define IFE_CO5_TXLPF_SEC1		(BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)
#define IFE_CO5_RXLPF				(2)
	#define IFE_CO5_RXLPF_MISC	    (BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25+BIT24+BIT23+BIT22+BIT21)
	#define IFE_CO5_RXLPF_FC13MS    (BIT20)
	#define IFE_CO5_RXLPF_PD	    (BIT19)
	#define IFE_CO5_RXLPF_CURR_CTL  (BIT18+BIT17+BIT16)
	#define IFE_CO5_RXLPF_SEC2		(BIT15+BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	#define IFE_CO5_RXLPF_SEC1		(BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)
#define IFE_CO5_TXVGA				(3)
	#define IFE_CO5_TXVGA_CUR_C		(BIT12+BIT11)
	#define IFE_CO5_TXVGA_PD		(BIT10)
	#define IFE_CO5_TXVGA_CUR_CTL	(BIT9+BIT8+BIT7)
	#define IFE_CO5_TXVGA_POLY_CUR_CTL	(BIT6+BIT5+BIT4)
	#define IFE_CO5_TXVGA_GAIN_CTL	(BIT3+BIT2+BIT1+BIT0)

#define IFE_CO5_PGA1				(4)
	#define IFE_CO5_PGA12_MISC		(BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25+BIT24+BIT23+BIT22+BIT21+BIT20)
	#define IFE_CO5_PGA12_CURR_CTL	(BIT19+BIT18+BIT17)
	#define IFE_CO5_PGA12_PD		(BIT16)
	#define IFE_CO5_PGA12_GAIN		(BIT15+BIT14+BIT13)
	#define IFE_CO5_PGA11_BOOST		(BIT12)
	#define IFE_CO5_PGA11_PD		(BIT11)
	#define IFE_CO5_PGA11_CURR_CTL	(BIT10+BIT9+BIT8)
	#define IFE_CO5_PGA11_MISC		(BIT7+BIT6+BIT5+BIT4)
	#define IFE_CO5_PGA11_GAIN		(BIT3+BIT2+BIT1+BIT0)
#define IFE_CO5_PGA2				(5)
	#define IFE_CO5_PGA2_MISC 		(BIT15+BIT14+BIT13+BIT12+BIT11)
	#define IFE_CO5_PGA2_INP_SEL	(BIT10+BIT9+BIT8+BIT7)
	#define IFE_CO5_PGA2_CURR_CTL	(BIT6+BIT5+BIT4)
	#define IFE_CO5_PGA2_PD		(BIT3)
	#define IFE_CO5_PGA2_GAIN		(BIT2+BIT1+BIT0)
#define IFE_CO5_RXHPF				(6)
	#define IFE_CO5_RXHPF_MISC_0	(BIT29)
	#define IFE_CO5_RXHPF_FC2		(BIT28)
	#define IFE_CO5_RXHPF_PD		(BIT27)
	#define IFE_CO5_RXHPF_CURR_CTL	(BIT26+BIT25+BIT24)
	#define IFE_CO5_RXHPF_F_CTL		(BIT23+BIT22+BIT21+BIT20+BIT19+BIT18+BIT17+BIT16)
	#define IFE_CO5_RXHPF_G_CTL		(BIT15+BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	#define IFE_CO5_RXHPF_CTL		(BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)
	
#define IFE_CO5_BUF_BIAS			(7)
	#define IFE_CO5_BUF_BIAS_RXEBUF_CUR_C			(BIT24+BIT23)
	#define IFE_CO5_BUF_BIAS_RXEBUF_CUR_CTL			(BIT22+BIT21+BIT20)
	#define IFE_CO5_BUF_BIAS_RXEBUF_POLY_CUR_CTL	(BIT19+BIT18+BIT17)
	#define IFE_CO5_BUF_BIAS_RXEBUF_PD				(BIT16)
	#define IFE_CO5_BUF_BIAS_RXOBUF_CUR_CTL			(BIT12+BIT11+BIT10)
	#define IFE_CO5_BUF_BIAS_RXOBUF_PD				(BIT9)
	#define IFE_CO5_BUF_BIAS_TXVCM_CTL				(BIT5+BIT4+BIT3)
	#define IFE_CO5_BUF_BIAS_RXVCM_CTL				(BIT2+BIT1+BIT0)

	

#define IFE_10050_REVID      	(0x24)
#define IFE_100100_REVID      	(0x34)
#define IFE_CO3_REVID      		(0x74)
#define IFE_CO3_EXT_LD_REVID      		(0x75)
#define IFE2_REG_0_DEFAULT      (0x1300F0F0)
#define IFE_CO5					(0xd10)
#define IFE_CPE5_DEV_ID             (0xE10)



#define AFE_CO3				(0xb10)
#define AFE_CO5				(0xc10)
#define AFE_IFE_CPE5		IFE_CPE5_DEV_ID


#define AFE_HLD_RDWR_CMD            (0x19)      // GLOBAL Reg
    #define HLD_REG_RD              (BIT31)
    #define HLD_REG_WR              (BIT30)
    #define HLD_NUM                 (BIT0)

#define AFE_HLD_REG_RD_WR_STAT      (0x1A)      // GLOBAL Reg
    #define HLD_STAT                (BIT31)
    #define WR_DATA                 (0x0FFF0000) //27:16
    #define RD_DATA                 (0x00000FFF) //11:0
	
	
	
	
/****************************  IFE-CPE5/HLD  Internal Registers   *****************************/
#define IFE_CPE5_TUNER               (0x15)
	 #define IFE_CPE5_TUNER_REG_MISC  (0xff)

#define IFE_CPE5_TXLPF4              (0X16)
	 #define IFE_CPE5_TXLPF4_MISC     (BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25+BIT24+BIT23+BIT22+BIT21)
	 #define IFE_CPE5_TXLPF4_PD    	  (BIT19)
	 #define IFE_CPE5_TXLPF4_FC13MS   (BIT20)
	 #define IFE_CPE5_TXLPF4_CURR_CTL (BIT18+BIT17+BIT16)
	 #define IFE_CPE5_TXLPF4_TUNE2    (BIT15+BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	 #define IFE_CPE5_TXLPF4_TUNE1    (BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)
		  #define LPF_FC_13_CTT           (0x15846)
		  #define LPF_FC_31_CTT           (0x21b0a)

#define IFE_CPE5_RXLPF4               (0X17)
	 #define IFE_CPE5_RXLPF4_MISC     (BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25+BIT24+BIT23+BIT22+BIT21)
	 #define IFE_CPE5_RXLPF4_FC9MS    (BIT20)
        #define LPF4_FC_19             (0)
        #define LPF4_FC_9              (1)
	 #define IFE_CPE5_RXLPF4_PD       (BIT19)
	 #define IFE_CPE5_RXLPF4_CURR_CTL (BIT18+BIT17+BIT16)
	 #define IFE_CPE5_RXLPF4_TUNE2    (BIT15+BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	 #define IFE_CPE5_RXLPF4_TUNE1    (BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)
	  	  #define LPF4_FC_9_CTT 	          (0x2709b)
		  #define LPF4_FC_19_CTT           (0x65c6c)

#define IFE_CPE5_RXLPF2              (0X18)
	 #define IFE_CPE5_RXLPF2_MISC     (BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25+BIT24+BIT23+BIT22+BIT21)
	 #define IFE_CPE5_RXLPF2_PD       (BIT19)
	 #define IFE_CPE5_RXLPF2_CURR_CTL (BIT18+BIT17+BIT16)
	 #define IFE_CPE5_RXLPF2_TUNE2    (BIT15+BIT14+BIT13+BIT12+BIT11+BIT10+BIT9+BIT8)
	 #define IFE_CPE5_RXLPF2_TUNE1    (BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)
	  	  #define LPF2_FC_13_CTT 	  		(0x15846)
		  #define LPF2_FC_23_CTT       		(0x21b0a)

#define IFE_CPE5_TXEBUF_TXVGA        (0x1d)
	 #define IFE_CPE5_TXEBUF_MISC      (BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25)
	 #define IFE_CPE5_TXEBUF_CUR_C     (BIT24+BIT23)
	 #define IFE_CPE5_TXEBUF_CURR_CTL  (BIT22+BIT21+BIT20)
	 #define IFE_CPE5_TXEBUF_POLY_CURR_CTL (BIT19+BIT18+BIT17)
	 #define IFE_CPE5_TXEBUF_PD        (BIT16)

	 #define IFE_CPE5_TXVGA_MISC      (BIT15+BIT14)
	 #define IFE_CPE5_TXVGA_CUR_C     (BIT13+BIT12+BIT11)
	 #define IFE_CPE5_TXVGA_PD        (BIT10)
	 #define IFE_CPE5_TXVGA_CURR_CTL  (BIT9+BIT8+BIT7)
	 #define IFE_CPE5_TXVGA_POLY_CURR_CTL (BIT6+BIT5+BIT4)
	 #define IFE_CPE5_TXVGA_GAIN_CTL  (BIT3+BIT2+BIT1+BIT0)

#define IFE_CPE5_PGA1                (1)
	 #define IFE_CPE5_PGA12_MISC      (BIT31+BIT30+BIT29)
	 #define IFE_CPE5_PGA12_CURR_CTL  (BIT28+BIT27+BIT26)
	 #define IFE_CPE5_PGA12_PD        (BIT25)
	 #define IFE_CPE5_PGA12_GAIN      (BIT24+BIT23+BIT22)
	 #define IFE_CPE5_PGA11_BYHPF     (BIT21)
	 #define IFE_CPE5_PGA11_PD        (BIT20)
	 #define IFE_CPE5_PGA11_1_CURR_CTL  (BIT19+BIT18+BIT17)
	 #define IFE_CPE5_PGA11_2_CURR_CTL  (BIT16+BIT15+BIT14)
	 #define IFE_CPE5_PGA11_MISC      (BIT13+BIT12+BIT11+BIT10)
	 #define IFE_CPE5_PGA11_GAIN      (BIT9+BIT8+BIT7+BIT6)
	 #define IFE_CPE5_PGA11_HPTUNE    (BIT5+BIT4+BIT3+BIT2+BIT1+BIT0)
#define IFE_CPE5_PGA2                (8)
	 #define IFE_CPE5_PGA2_MISC       (BIT15+BIT14+BIT13+BIT12+BIT11)
	 #define IFE_CPE5_PGA2_INP_SEL    (BIT10+BIT9+BIT8+BIT7)
		  #define SEL_276             (0x01)
		  #define SEL_138             (0x02)
		  #define SEL_RXLPF4          (0x04)
		  #define SEL_BYPASS          (0x08)
	 #define IFE_CPE5_PGA2_CURR_CTL   (BIT6+BIT5+BIT4)
	 #define IFE_CPE5_PGA2_PD     	(BIT3)
	 #define IFE_CPE5_PGA2_GAIN       (BIT2+BIT1+BIT0)

#define IFE_CPE5_BUF_BIAS            (0x13)
	 #define IFE_CPE5_BUF_BIAS_RXEBUF_MISC          	(BIT31+BIT30+BIT29+BIT28+BIT27+BIT26+BIT25)
	 #define IFE_CPE5_BUF_BIAS_RXEBUF_CURR_C          (BIT24+BIT23)
	 #define IFE_CPE5_BUF_BIAS_RXEBUF_CURR_CTL        (BIT22+BIT21+BIT20)
	 #define IFE_CPE5_BUF_BIAS_RXEBUF_POLY_CURR_CTL   (BIT19+BIT18+BIT17)
	 #define IFE_CPE5_BUF_BIAS_RXEBUF_PD              (BIT16)
	 #define IFE_CPE5_BUF_BIAS_RXOBUF_EBUF_MISC       (BIT15+BIT14+BIT13)
	 #define IFE_CPE5_BUF_BIAS_RXOBUF_CURR_CTL        (BIT12+BIT11+BIT10)
	 #define IFE_CPE5_BUF_BIAS_RXOBUF_PD              (BIT9)
	 #define IFE_CPE5_BUF_BIAS_TXVCM_MISC             (BIT8+BIT7+BIT6)
	 #define IFE_CPE5_BUF_BIAS_TXVCM_CTL              (BIT5+BIT4+BIT3)
	 #define IFE_CPE5_BUF_BIAS_RXVCM_CTL              (BIT2+BIT1+BIT0)


	



//TEST DEFINES
#define NEW_PGA_VALUE (0x6D00F0F0) // bits 30:24 are PGA
#define AFE_MAX_RW_REPEAT		(100)

/************** FOR LBIST TEST *************************/
#define DFE_RX_EN    	0xe0058500

#define DDR_TEST_CTRL   0xe00c0c00
#define DDR_LBIST_DATA0 0xe00c0c04
#define DDR_LBIST_DATA1 0xe00c0c08
#define DDR_LBIST_CMP   0xe00c0c0c
#define DDR_LBIST_STAT  0xe00c0c10

#define AFE_CO3             (0xb10)
#define AFE_CO5             (0xc10)


#define WHICH_AFE(p)    ((p)/NUM_PORTS_PER_AFE)

#define s8				INT8
#define u8				UINT8
#define s16				INT16
#define u16				UINT16
#define s32				INT32
#define u32				UINT32


/************** GLOBAL VARIABLES *************************/

/************** EXTERN FUNCTIONS AND VARIABLES ***********/
int testPIORead1 (int BmeNum, unsigned long addr);
void testPIOWrite (int BmeNum, unsigned long addr, unsigned long data);
int gpioHldTest(int bmeNum, int port);
int hldTest(int bmeNum, int port);

/*********************************************************/
/*              LOCAL FUNCTION PROTOTYPES                */
/*********************************************************/
// test functions
int chkAfeRevId (int bmeNum, int afeNum);
int chkIfeType (int bmeNum, int port);
int chkIfeRevId (int bmeNum, int port);
int chkIfePGArdrw (int bmeNum, int port);
// afe & ife access functions
int AfeIsBusy (int bmeNum);
int AfeVerAccess (int bmeNum);
int afeWr (int bmeNum, int port, int addr, int data);
int afeRd (int bmeNum, int port, int addr);
int afeCal (int bmeNum, int port);
void dumpCoeff (int bmeNum, int port, int len);
void dumpRegs (int bmeNum, int port);
int ifeRd (int bmeNum, int port, int addr);
void ifeWr (int bmeNum, int port, int addr, int data);
void retuneIfe (int bmeNum, int port);
int ddr_lbist (int bmeNum, int port);
void hldWrite (int bmeNum, int port, int data);
void serHldWrite (int bmeNum, int port, int data);
int hldRead (int bmeNum, int port);
int serHldRead (int bmeNum, int port);

void gpioHldWrite(int bmeNum, int port, u16 inData);
unsigned int gpioHldRead(int bmeNum, int port);
void clearIfeRdwrStat (int bmeNum, int port);



int afeId [2] [2]= {{-1,-1},{-1,-1}};
int ifeId [2] [8]=   {{-1,-1,-1,-1,-1,-1,-1,-1},{-1,-1,-1,-1,-1,-1, -1 ,-1}};
int ifeType [2] [8]= {{-1,-1,-1,-1,-1,-1,-1,-1},{-1,-1,-1,-1,-1,-1, -1 ,-1}};

static int iIfeRegMask = (int) BIT0 | BIT1 | BIT2 | BIT3 | BIT4;


/*********************************************************/
/*            EXPORTED FUNCTION DEFINITIONS              */
/*********************************************************/
// AfeCO3test:
// input bme number and afe number (0 or 1)
// tests AFE register read/write
// returns -1 if test fails
int AfeCO5test (int bmeNum, int afeNum)
{
    int retVal=0, port=0;


    retVal = chkAfeRevId (bmeNum, afeNum);
	afeId [bmeNum] [afeNum] = retVal;
	if (afeId[bmeNum] [afeNum]  == AFE_CO3)
		DBG0(("AFE CO3 FOUND on AFE%d\n",afeNum))
	else if (afeId[bmeNum] [afeNum] == AFE_CO5)
		DBG0(("AFE CO5 FOUND on AFE%d\n",afeNum))
	else if (afeId[bmeNum] [afeNum] == AFE_IFE_CPE5)
		DBG0(("IFE CPE5 FOUND\n"))
	else
	{
		DBG0(("**** AFE %d NOT RECOGNIZED ****",afeNum))
		return ERROR;
	}




    DBG2(("Bme %d Afe %d:\n", bmeNum, afeNum))

	// scratchpad write to the misc reg
	afeWr (bmeNum, port, AFE_MISC, 0xaaaa);
	if (afeRd (bmeNum, port, AFE_MISC) != 0xaaaa)
		DBG2(("Write verify AFE_MISC register failed, Reg 0x12 not = 0xaaaa\n"))
	else
		DBG2(("Write verify AFE_MISC register passed, Reg 0x12 correct\n"))

	afeWr (bmeNum, port, AFE_MISC, 0x5555);
	if (afeRd (bmeNum, port, AFE_MISC) != 0x5555)
		DBG2(("Write verify AFE_MISC register failed, Reg 0x12 not = 0x5555\n"))
	else
		DBG2(("Write verify AFE_MISC register passed, Reg 0x12 correct\n"))

    if (retVal != -1 /* ie, not failure */)
    {
		// get and save ife types
        chkIfeType (bmeNum, afeNum*4 + 0);
#ifndef CPE_50
        chkIfeType (bmeNum, afeNum*4 + 1);
        chkIfeType (bmeNum, afeNum*4 + 2);
        chkIfeType (bmeNum, afeNum*4 + 3);
#endif
    }
    if (retVal != -1 /* ie, not failure */)
    {
        DBG2(("Calibrating AFE ADC & DAC: "))
        for (port = afeNum * NUM_PORTS_PER_AFE;
            port < (afeNum+1) * NUM_PORTS_PER_AFE; port++)
        {
            if (-1 == (retVal = afeCal (bmeNum, port)))
                break;
        }

        if (retVal != -1) {
            DBG2(("AFE CAL TEST PASSED on port %d\n",port))
        } else {
            DBG0(("AFE CAL TEST FAILED on port %d\n",port))
        }
    }

    if (retVal != -1)
        return 0;

    return -1;
}


int IfeTestCO5 (int bmeNum, int port)
{
    int retVal;
	int which_afe = WHICH_AFE(port);
	int err;


	DBG2(("Testing IFE Port: %x. ", port))
    DBG2(("Bme %d Afe %d Ife %d:\n",
        bmeNum, port/NUM_PORTS_PER_AFE, port%NUM_PORTS_PER_AFE))



    retVal = chkIfeRevId (bmeNum, port);

    if (retVal != -1 /* ie, not failure */)
    {
        retVal = chkIfePGArdrw (bmeNum, port);
    }
    if (retVal != -1 /* ie, not failure */)
    {
        DBG2(("Retuning IFE.. "))
        retuneIfe (bmeNum, port);
        DBG2(("done.\n"))
    }

    if (retVal != -1)
    {
        DBG0(("PORT %d IFE REG R/W TEST PASSED\n", port))
    } else {
        DBG0(("**** PORT %d IFE REG R/W TEST FAILED ****\n", port))
		retVal = ERROR;
    }

	if (afeId[bmeNum] [which_afe]  == AFE_CO3)
	{

		err = gpioHldTest(bmeNum, port);
		if (err)
		{
			printf("HLD TEST Failed Port %d\n", port);
			retVal = ERROR;
		}


	}
	else
	{

		err = hldTest(bmeNum, port);
		if (err)
		{
			printf("HLD TEST Failed Port %d\n", port);
			retVal = ERROR;
		}


	}

	return retVal;

}



//#endif

int lbist_loop (int bmeNum)
{
  int test_stat = 0;

     DBG1(("Bme %d LBIST Test:\n", bmeNum))

     DBG1(("Channel-0 DDR I/F "))
 	 test_stat |= ddr_lbist (bmeNum, 0);
#ifdef CPE_50
	 return test_stat;
#endif

     DBG1(("Channel-1 DDR I/F "))
	 test_stat |= ddr_lbist (bmeNum, 1);

     DBG1(("Channel-2 DDR I/F "))
	 test_stat |= ddr_lbist (bmeNum, 2);

     DBG1(("Channel-3 DDR I/F "))
	 test_stat |= ddr_lbist (bmeNum, 3);

     DBG1(("Channel-4 DDR I/F "))
 	 test_stat |= ddr_lbist (bmeNum, 4);
     DBG1(("Channel-5 DDR I/F "))
 	 test_stat |= ddr_lbist (bmeNum, 5);
     DBG1(("Channel-6 DDR I/F "))
 	 test_stat |= ddr_lbist (bmeNum, 6);
     DBG1(("Channel-7 DDR I/F "))
 	 test_stat |= ddr_lbist (bmeNum, 7);
	 return test_stat;
}


static struct 
{
	UINT32 dfe;
	UINT32 af;		
} dfe_af_base_address[8] = 
{
  {0x0, 0x0}, 
  {0x2000, 0x1000},
  {0x4000, 0x2000},
  {0x6000, 0x3000},
  {0x10000000, 0x10000000},
  {0x10002000, 0x10001000},
  {0x10004000, 0x10002000},
  {0x10006000, 0x10003000}
};

int ddr_lbist1 (int bmeNum, int port, int testdata, int expectdata)
{
	int test_data0 = 0;
	int test_data1 = 0;
	int cmp_data = 0;
	int read_data = 0;
	UINT32 Flag = 0;
	UINT32 dfe_base_addr, af_base_addr;
    int which_afe = WHICH_AFE(port);

	dfe_base_addr = dfe_af_base_address[port].dfe;
	af_base_addr = dfe_af_base_address[port].af;
	
	afeWr(bmeNum, port, AFE_DIGITAL_TEST, 1);
	if (afeId[bmeNum][which_afe]  == AFE_CO5)
		afeWr(bmeNum, port, AFE_PWR_DOWN, BIT24+BIT25);
	else
		afeWr(bmeNum, port, AFE_PWR_DOWN, 0);
	testPIOWrite(bmeNum,(DFE_RX_EN | af_base_addr) , 0x00000101);

	test_data0 = testdata;
	test_data1 = 0x0000965A;
	testPIOWrite(bmeNum,(DDR_LBIST_DATA0 | dfe_base_addr),test_data0);
	testPIOWrite(bmeNum,(DDR_LBIST_DATA1 | dfe_base_addr),test_data1);
	cmp_data =  (expectdata & 0x00003fff)>>2;
	testPIOWrite(bmeNum,(DDR_LBIST_CMP | dfe_base_addr), ((cmp_data<<8) | 0x00000000));
	testPIOWrite(bmeNum,(DDR_LBIST_CMP | dfe_base_addr), ((cmp_data<<8) | 0x00000001));
	taskDelay(2);
	testPIOWrite(bmeNum,(DDR_TEST_CTRL | dfe_base_addr),0x00000001);

	taskDelay(20);

	read_data = testPIORead1 (bmeNum,(DDR_LBIST_STAT | dfe_base_addr));
	if ((read_data & 0x00000001) == 1) {
		Flag = 1;
	} else {
		Flag = 0;
	}
	return(Flag);
}

void ddr_lbist_walk1_test (int bmeNum, int port)
{
   int i;
   int data, cmp;
   int retcode;
   
   DBG1(("Bme %d LBIST Walk 1 Test:\n", bmeNum))
   DBG1(("Channel-%d DDR I/F\n", port))
   
   data = 0x0004;
   for (i=2; i<14; i++)
   {
       cmp = data;
	if ((retcode = ddr_lbist1 (bmeNum, port, data, cmp)) == 0)
	{
		DBG1(("data = 0x%04x, result = 0x%04x : PASSED\n", data, cmp));
	}
	else
	{
	   	for (cmp=0; cmp<0x00003fff; cmp+=4)
	   	{
			if ((retcode = ddr_lbist1 (bmeNum, port, data, cmp)) == 0)
			{
				DBG1(("data = 0x%04x, result = 0x%04x : FAILED\n", data, cmp));
				break;
			}
	   	}
	}
	data <<=1;
   }
}
void ddr_lbist_walk0_test (int bmeNum, int port)
{
   int i;
   int data, cmp;
   int retcode;

   DBG1(("Bme %d LBIST Walk 0 Test:\n", bmeNum))
   DBG1(("Channel-%d DDR I/F\n", port))
   
   data = 0x0004;
   for (i=2; i<14; i++)
   {
       cmp = data;
	if ((retcode = ddr_lbist1 (bmeNum, port, ~data, ~cmp)) == 0)
	{
		DBG1(("data = 0x%04x, result = 0x%04x : PASSED\n", ~data, ~cmp));
	}
	else
	{
	   	for (cmp=0; cmp<0x00003fff; cmp+=4)
	   	{
			if ((retcode = ddr_lbist1 (bmeNum, port, ~data, ~cmp)) == 0)
			{
				DBG1(("data = 0x%04x, result = 0x%04x : FAILED\n", ~data, ~cmp));
				break;
			}
	   	}
	}
	data <<=1;
   }
}

void ddr_walk_test (int bmeNum, int port )
{
    int i;

    if (port < 0)
    {
		for (i=0; i<8; i++)
		{
            ddr_lbist_walk1_test (bmeNum, i);
            ddr_lbist_walk0_test (bmeNum, i);
        }
    }
    else
    {
        ddr_lbist_walk1_test (bmeNum, port);
        ddr_lbist_walk0_test (bmeNum, port);
    }
};	


/*********************************************************/
/*              LOCAL DIAG TEST FUNCTIONS                */
/*********************************************************/

int ddr_lbist (int bmeNum, int port)
{
	if (ddr_lbist1 (bmeNum, port, 0x0000F0A5, 0x0000F0A5) == 1)
	{
		DBG0(("**** PORT %d FAILED LBIST ****\n", port))
		return 1;
	}
	DBG1(("PASSED\n"))
	return 0;
}


// chkAfeRevId:
// input bme number and afe number
// prints afe version if afe read successful
// prints test failure if read fails
// returns afe version (13 bits) or -1
int chkAfeRevId (int bmeNum, int afeNum)
{
    int afeVer = -1, port;
 
    // read afe rev id
    for (port = afeNum * NUM_PORTS_PER_AFE;
        port < (afeNum+1) * NUM_PORTS_PER_AFE; port++)
    {
        if (-1 == (afeVer = afeRd (bmeNum, port, AFE_VERSION) & 0xfff))
            break;
    }

    if (afeVer == -1)
    {
        DBG0(("AFE Version read failed on port %d\n", port))
    }
    else
    {
        DBG2(("AFE Version is 0x%3x\n", afeVer))
    }

    return (afeVer);
}

// chkIfeType:
// input bme number and port number
// prints ife type if afe read successful
// prints test failure if read fails
// returns ife type (0 or 1) or -1
int chkIfeType (int bmeNum, int port)
{
int afeVer;

	if ((afeVer = afeRd (bmeNum, port, AFE_VERSION)) ==IFE_CPE5_DEV_ID)
	{

		ifeId [bmeNum] [port] = IFE_CPE5_DEV_ID;
		ifeType [bmeNum] [port] = afeVer;
		DBG2(("IFE CPE5 Recognized\n"));
		return afeVer;
	}


    // read ife type (ife2 or ife-co3 or ife5) from AFE
	ifeType [bmeNum] [port] = afeRd (bmeNum, port, AFE_IFE_TYPE);
	if ( ifeType [bmeNum] [port] == IFE_CO50_TYPE )
		(ifeId [bmeNum] [port] = IFE_CO5);


    if (ifeType [bmeNum] [port] == -1)
    {
        DBG0(("Bme %d Afe %d: Couldnt read Ife type from AFE\n", bmeNum, port/NUM_PORTS_PER_AFE));
    }
    else
    {
		// if we're a afe_c05 then pin equaling 1 = IFE_CO5
        if (ifeType[bmeNum] [port]  & 0x1)
			DBG0(("Bme %d Afe %d: AFE says IFE %d is IFE-CO5\n", bmeNum, port/NUM_PORTS_PER_AFE, port))
        else
            DBG0(("Bme %d Afe %d: AFE says IFE %d is IFE2\n", bmeNum, port/NUM_PORTS_PER_AFE, port))
    }

    return (ifeType [bmeNum] [port]);
}

// chkIfeRevId:
// input bme number and port number
// prints ife version if ife read successful, ie REvID = 0x24
// prints test failure if read fails
// returns ife version (8 bits) or -1
int chkIfeRevId (int bmeNum, int port)
{
    int ifeVer;
	
	/*
		if its an afe co5 then see whether the ife type bit is hi. if so
		its a ife5 else an ife2. If its an ife2 then find out what type of ife2
	*/

	if ((ifeVer = afeRd (bmeNum, port, AFE_VERSION)) ==IFE_CPE5_DEV_ID)
	{
		DBG2(("IFE CPE5 Recognized\n"));
		return ifeVer;
	}



	if (afeId [bmeNum] [port/4] == -1)
	{
		printf("AFE Id not initialized\n");
		return-1;
	}
	if (ifeType [bmeNum] [port] == -1)
	{
		printf("IFE Type not initialized\n");
		return -1;
	}

	if ((afeId [bmeNum] [port/4] == AFE_CO5) || (afeId [bmeNum] [port/4] == AFE_CO3))
	{

		// First test if it is a ife_co5
		if (ifeType [bmeNum] [port] == IFE_CO50_TYPE)
		{
			// go back if IFE_CO5
			ifeVer = ifeRd (bmeNum, port, IFE_CO5_REV_ID);
			if ((ifeVer & IFE_REV_ID_MASK ) == IFE_CO5)
			{
				DBG2(("IFE REvID = IFE_CO5\n"))
				return ifeVer;
			}
		}
		//else its a ife2 so just continue
	}


    ifeVer = ifeRd (bmeNum, port, IFE2_REG_1);
    DBG2(("IFE RevID check: "))
    if (ifeVer == -1)
    {
        DBG0(("port %d ERROR - Couldnt read Ife RevID\n", port))
    }
    else
    {
        ifeVer = (ifeVer & IFE2_REVID_MASK) >> 8;
        if (ifeVer == IFE_10050_REVID  ||
            ifeVer == IFE_100100_REVID ||
            ifeVer == 0x75 ||
            ifeVer == IFE_CO3_REVID )
        {
            DBG2(("IFE REvID = 0x%x passed\n", ifeVer))
        }
        else
        {
            DBG0(("port %d WRONG IFE REvID 0x%x\n", port, ifeVer))
            //return -1;
        }
    }
    return ifeVer;
}


// chkIfePGArdrw:
// input bme number and port number
// write new PGA value, read back to verify
// write default PGA value, read back to verify
// prints test failure if PGA write unsuccessful
// returns 0 (success) or -1
int chkIfePGArdrw (int bmeNum, int port)
{
    int ifePgaVal = 0;
	int reg ;

	// no need for this test in IFE CPE5 since ife is inside afe
	if ((ifeId [bmeNum] [port] & IFE_REV_ID_MASK ) == IFE_CPE5_DEV_ID)  
		return 0;


	if ((ifeId [bmeNum] [port] & IFE_REV_ID_MASK ) == IFE_CO5)  
		reg = IFE_CO5_COM_MISC;
	else
		reg = IFE2_REG_0;


    DBG2(("PGA setting read/write: "))
    ifeWr (bmeNum, port, reg, NEW_PGA_VALUE);
    ifePgaVal = ifeRd (bmeNum, port, reg);

    if (ifePgaVal != NEW_PGA_VALUE)
    {
        DBG0(("port %d ERROR - couldnt write Reg 0 PGA 0x%x, read 0x%x\n",
                    port, NEW_PGA_VALUE, ifePgaVal))
        return -1;
    }
    else
    {
        DBG2(("wrote Reg 0 PGA 0x%x\n", NEW_PGA_VALUE))
    }


    ifeWr (bmeNum, port, reg, IFE2_REG_0_DEFAULT);
    ifePgaVal = ifeRd (bmeNum, port, reg);

    if (ifePgaVal != IFE2_REG_0_DEFAULT)
    {
        DBG0(("port %d ERROR - couldnt write Reg 0 PGA 0x%x, read 0x%x\n",
                    port, IFE2_REG_0_DEFAULT, ifePgaVal))
        return -1;
    }
    else
    {
        DBG2(("wrote Reg 0 PGA setting %d\n", IFE2_REG_0_DEFAULT))
        DBG2(("passed\n"));
    }

    return 0;
}


/*********************************************************/
/*              LOCAL AFE IFE ACCESS FUNCTIONS           */
/*********************************************************/

/*
************************************************************************
	Function: AFE is Busy

	int AfeIsBusy (int bmeNum)
	
   Description:
		This function verifies that Busy Bit within the PIO_AFE_RDWR_STAT 
		resister is clear.
		
		Input: 
			None.
			
		Output:
			1 : if Busy bit is clear
		   -1: if busy bit is set

************************************************************************
*/
int AfeIsBusy (int bmeNum)
{
 unsigned char d=0xff; 
 int ret, i;

	i = 1000;
	ret = TRUE;

	while (d)
	{
		if ( --i == 0 )
		{
			IK_PRINTF("\nAFE interface is busy.....\n");
			ret = FALSE;
			break;
		}

		d = testPIORead1 (bmeNum, PIO_AFE_RDWR_STAT);
		d &= AFE_CMD_BUSY;
        BUP_DELAY_MS(1);
	}

	return (ret);
}


/*
************************************************************************
	Function: AFE Verify Access

	int AfeVerAccess (int bmeNum)
	
   Description:
		This function verifies that the last access to AFE was successfull 
		by monitoring (10,000 trials) the AFE_CMD_PASS bit within the 
		PIO_AFE_RDWR_STAT register. allows a 16 bits read access from 
		AFE_CO30.
		
		Input: 
			None.
			
		Output:
			1 : Pass bit is set
			-1: Pass bit is clear
************************************************************************
*/
int AfeVerAccess (int bmeNum)
{
 unsigned char d=0;
 int i = 10000;
 int status = TRUE;

	while (!d)
	{
		if ( --i == 0 )
		{
			IK_PRINTF("\nfailed to access afe....\n");
			status = FALSE;
			return (status);
		}

		d = testPIORead1 (bmeNum, PIO_AFE_RDWR_STAT);
		d &= AFE_CMD_PASS;
	}

	return (status);
}




/*
************************************************************************
	Function: AFE Write

	void afeWr (bmeNum, int port, int addr, int data)
	
   Description:
		This function allows a write access to any AFE registers. This function 
		performs the following tasks for each AFE write.
		
		> clear the rdwr_stat reg
		> write data into D4-D7 (D7 has the most sign. byte)
		> perform write to write_data reg
		> construct rdwr_cmd vlaue w/ port and addr
		> write rdwr_cmd value to D4-D7 (D7 has the most sign. byte)
		> perform a write to wrrd_cmd reg
		> verify that write took place
		
		Input: 
			port: 0-3
			addr; AFE register number
			data: data need to be written into the given register
			
		Output:
			None.
************************************************************************
*/
int afeWr (int bmeNum, int port, int addr, int data)
{
    int st, cmd_val;

	st = AfeIsBusy (bmeNum);
  	if ( (port >= 0) && (port < MAX_PORT_PER_BME) && (st == TRUE) )
	{
        // Clear the pass/fail bits
		//testPIOWrite (bmeNum, PIO_AFE_RDWR_STAT, 0x00); 
	
		// Write the data 
        testPIOWrite (bmeNum, PIO_AFE_WRITE_DATA, data);
	
		// construct the wrrd_cmd value 
		cmd_val = AFE_WR_REG + ((port/NUM_PORTS_PER_AFE) << 16) + ((port&3) << 8) + (addr & 0x1f);

        testPIOWrite (bmeNum, PIO_AFE_RDWR_CMD, cmd_val);

		// verify that write was successfull....
		st = AfeVerAccess (bmeNum);

	// clear stat register
	testPIOWrite (bmeNum, PIO_AFE_RDWR_STAT, AFE_CMD_PASS+AFE_CMD_FAIL); 

	}
    if (st != TRUE)
	{
		IK_PRINTF("\ncan't access afe via 'afeWr (bmeNum, port, addr, data)'");
		IK_PRINTF("\nport: %d  addr: %d , data: %x  status: %d\n", port, addr, data, st); 
	}
    return st;
}



/*
************************************************************************
	Function: AFE Read

	void afeRd (int bmeNum, int port, int addr)
	
   Description:
		This function allows a read access to any AFE registers. 		
		
		Input: 
			port: 0-3
			addr; AFE register number
			
		Output:
			32 bit register value
************************************************************************
*/
int afeRd (int bmeNum, int port, int addr)
{
    int st, cmd_val;
  
	st = AfeIsBusy (bmeNum);
	if ( (port >= 0) && (port < MAX_PORT_PER_BME) && (st == TRUE) )
	{
		// Clear the pass/fail bits
		//testPIOWrite (bmeNum, PIO_AFE_RDWR_STAT, 0x00); 
	  
		// construct the wrrd_cmd value 
		cmd_val = AFE_RD_REG + ((port/NUM_PORTS_PER_AFE) << 16) + (port << 8) + (addr & 0x1f);
  
        testPIOWrite (bmeNum, PIO_AFE_RDWR_CMD, cmd_val);

        BUP_DELAY_MS(1);
		// verify that write was successfull....
		st = AfeVerAccess (bmeNum);

		// clear stat register
		testPIOWrite (bmeNum, PIO_AFE_RDWR_STAT, AFE_CMD_PASS+AFE_CMD_FAIL); 

		// initiate a read...
		cmd_val = testPIORead1 (bmeNum, PIO_AFE_READ_DATA);

		// read the value from scr pad reg...
		return (cmd_val);
	}
	else
	{
		IK_PRINTF("\ncan't access afe via 'afeRd (bmeNum, port, addr)'");
		IK_PRINTF("\nbmeNum: %d port: %d  addr: %d status: %d\n",bmeNum, port, addr, st); 
		return (-1);
	}
}


/*
************************************************************************
	Function: Calibrate AFE
	
	Description:
		calibarte both dac and adc within the afe	for the given cal
		
		Input: 
			port: 0-3
			
		Output:
			1 : Pass
			-1: Fail
	
************************************************************************
*/
int afeCal (int bmeNum, int port)
{
 int calStatus, i;
	
 int which_afe = WHICH_AFE(port);


    afeWr(bmeNum, port, AFE_PWR_DOWN, BIT24+BIT25);

	afeWr (bmeNum, port, AFE_ADC_DAC_TEST, 0);

	/* initiate dac and followed by adc calibration */
	afeWr (bmeNum, port, AFE_CAL_DAC_CMD, CRQ_VDAC);
	BUP_DELAY_MS(1);
	afeWr (bmeNum, port, AFE_CAL_ADC_CMD, CRQ_VADC);
	BUP_DELAY_MS(1);

	i = 0;
	/* verify adc cal is completed....adc cal takes less cycles to complete */
	while(1) 
	{
		if (afeId[bmeNum][which_afe]  == AFE_CO5)
		{
			calStatus = afeRd (bmeNum, port, AFE_CAL_ADC_STAT) & (VADC_RDY_A | VADC_RDY_B);
			if(calStatus == (VADC_RDY_A | VADC_RDY_B))
				break;
		}
		else
		{
			calStatus = afeRd (bmeNum, port, AFE_CAL_ADC_STAT);
			if(calStatus & VADC_RDY)
				break;
		}
		if(i++ > AFE_MAX_RW_REPEAT)
		{
			IK_PRINTF("\nADC cal not done %x\n", calStatus);
			return (-1);
		}
		
	    BUP_DELAY_MS(1);
	}

	i = 0;
	/* verify dac cal is completed */
	while(1) {
        calStatus = afeRd (bmeNum, port, AFE_CAL_DAC_STAT);
		if(calStatus & VDAC_RDY)
		{
			break;
		}

		if(i++ > AFE_MAX_RW_REPEAT)
		{
			IK_PRINTF("\nDAC cal not done %x\n", calStatus);
			return (-1);
		}
		
	    BUP_DELAY_MS(1);
	}

	return (1);
}


/*
************************************************************************
	Function: Dump DAC/ADC Coeffs

	dumpCoeff (int bmeNum, int port, int len)
	
   Description:
		This function displays all DAC and ADC coefficients specified by len
		
		Input: 
			port: 0-3
			len: Number of Coefficients
			
		Output:
			None.

************************************************************************
*/
void dumpCoeff (int bmeNum, int port, int len)
{
 int calStatus, i;
 int which_afe = WHICH_AFE(port);

	calStatus =  afeRd (bmeNum, port, AFE_CAL_DAC_STAT);
	if ( calStatus & VDAC_RDY )
	{
		afeWr (bmeNum, port, AFE_ADC_DAC_TEST, TEST_DAC);

		IK_PRINTF("\nDAC coefficients (%d) port: %d\n", len, port);
		/* dump dac coeff */
		for (i=0 ; i<len ; i++)
		{
			afeWr (bmeNum, port, AFE_CAL_DAC_CMD, CRQ_VDAC);
			IK_PRINTF(" 0x%x", afeRd (bmeNum, port, AFE_DAC_COEF) & DAC_COEF_MASK);
		}
		if (afeId[bmeNum][which_afe]  == AFE_CO5)
		{
			calStatus = afeRd (bmeNum, port, AFE_CAL_ADC_STAT) & (VADC_RDY_A | VADC_RDY_B);
			if(calStatus == (VADC_RDY_A | VADC_RDY_B))
				afeWr (bmeNum, port, AFE_ADC_DAC_TEST, TEST_ADC_A | TEST_ADC_B);
			else
				IK_PRINTF("\n ADC calibration in progress 0x%x port: %d\n", calStatus, port);

		}
		else
		{
			calStatus = afeRd (bmeNum, port, AFE_CAL_ADC_STAT);
			if ( calStatus & VADC_RDY )
				afeWr (bmeNum, port, AFE_ADC_DAC_TEST, TEST_ADC);
			else
				IK_PRINTF("\n ADC calibration in progress 0x%x port: %d\n", calStatus, port);

		}

		IK_PRINTF("\nADC coefficients (%d) port: %d\n", len, port);
		/* dump adc coeff */
		for (i=0 ; i<len ; i++)
		{
			afeWr (bmeNum, port, AFE_CAL_ADC_CMD, CRQ_VADC);
			IK_PRINTF(" 0x%x", afeRd (bmeNum, port, AFE_ADC_COEF) & ADC_COEF_MASK);
		}

		afeWr (bmeNum, port, AFE_ADC_DAC_TEST, 0);
	}
	else
	{
		IK_PRINTF("\n DAC calibration in progress 0x%x port: %d\n", calStatus, port);
	}
}


/*
************************************************************************
	Function: Dump AFE Registers

	dumpRegs (int bmeNum, int port)
	
   Description:
		This function displays all the AFE registers
		
		Input: 
			port: 0-3
			
		Output:
			None.

************************************************************************
*/
void dump_IFE_CPE5_Regs (int bmeNum, int port)
{

	 int i;
	 static char afeRegs [48] = 	{AFE_VERSION,
									 AFE_IFE_RETUNE_CTRL,
									 AFE_BAND_GAP_CTRL,
									 AFE_ADC_DAC_MODE,
									 AFE_PWR_DOWN,
									 AFE_VCXO_CTRL,
									 AFE_ADC_COEF,
									 AFE_DAC_COEF,
						  			 AFE_ADC_BIAS,
									 AFE_DAC_BIAS,
									 AFE_VCXO_CNTRL_2,
									 AFE_CAL_DAC_CMD,
									 AFE_CAL_ADC_CMD,
									 AFE_CAL_ADC_STAT,
									 AFE_CAL_DAC_STAT,
									 AFE_ADC_DAC_TEST,
									 AFE_ANALOG_TEST,
									 AFE_MISC,
									 AFE_DIGITAL_TEST,
									 AFE_HLD_RDWR_CMD,
									 AFE_HLD_REG_RD_WR_STAT,
									 AFE_ADC_B_OFFSET,
									 AFE_ADC_B_GAIN,
									 AFE_GPIO_RD_WD_DATA,
									 AFE_ADC_K1_K2,
									 AFE_ADC_K3_K4,
									IFE_CPE5_TUNER,
									 IFE_CPE5_TXLPF4,
									 IFE_CPE5_RXLPF4,
									 IFE_CPE5_RXLPF2,
									 IFE_CPE5_TXEBUF_TXVGA,
									 IFE_CPE5_PGA1,
									 IFE_CPE5_PGA2,
									 IFE_CPE5_BUF_BIAS
	 };

	 for (i = 0;i < 34;i++)
		  IK_PRINTF("\n [0x%02X]:   0x%08x", afeRegs [i], afeRd (bmeNum, port, afeRegs [i]));
}






void dumpRegs (int bmeNum, int port)
{
	int i;


	if ((ifeId [bmeNum] [port] & IFE_REV_ID_MASK ) == IFE_CPE5_DEV_ID)  
	{
		dump_IFE_CPE5_Regs (bmeNum, port);
		return;
	}

	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_VERSION, afeRd (bmeNum, port, AFE_VERSION));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_IFE_TYPE, afeRd (bmeNum, port, AFE_IFE_TYPE));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_BAND_GAP_CTRL, afeRd (bmeNum, port, AFE_BAND_GAP_CTRL));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_PLL_TEST, afeRd (bmeNum, port, AFE_PLL_TEST));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_PWR_DOWN, afeRd (bmeNum, port, AFE_PWR_DOWN));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_ADC_STAT, afeRd (bmeNum, port, AFE_ADC_STAT));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_ADC_BIAS, afeRd (bmeNum, port, AFE_ADC_BIAS));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_DAC_BIAS, afeRd (bmeNum, port, AFE_DAC_BIAS));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_CAL_ADC_CMD, afeRd (bmeNum, port, AFE_CAL_ADC_CMD));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_CAL_DAC_CMD, afeRd (bmeNum, port, AFE_CAL_DAC_CMD));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_CAL_ADC_STAT, afeRd (bmeNum, port, AFE_CAL_ADC_STAT));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_CAL_DAC_STAT, afeRd (bmeNum, port, AFE_CAL_DAC_STAT));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_ADC_DAC_TEST, afeRd (bmeNum, port, AFE_ADC_DAC_TEST));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_ANALOG_TEST, afeRd (bmeNum, port, AFE_ANALOG_TEST));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_MISC, afeRd (bmeNum, port, AFE_MISC));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_DIGITAL_TEST, afeRd (bmeNum, port, AFE_DIGITAL_TEST));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_IFE_RDWR_CMD, afeRd (bmeNum, port, AFE_IFE_RDWR_CMD));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_IFE_REG_RD_DATA, afeRd (bmeNum, port, AFE_IFE_REG_RD_DATA));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_IFE_REG_WR_DATA, afeRd (bmeNum, port, AFE_IFE_REG_WR_DATA));
	IK_PRINTF("\n [0x%02X]:   0x%04x", AFE_IFE_RDWR_STAT, afeRd (bmeNum, port, AFE_IFE_RDWR_STAT));
	IK_PRINTF("\n [0x%02X]:   0x%04x", 0x19, afeRd (bmeNum, port, 0x19));
	IK_PRINTF("\n [0x%02X]:   0x%04x", 0x1a, afeRd (bmeNum, port, 0x1a));
	IK_PRINTF("\n [0x%02X]:   0x%04x", 0x1b, afeRd (bmeNum, port, 0x1b));
	IK_PRINTF("\n [0x%02X]:   0x%04x", 0x1c, afeRd (bmeNum, port, 0x1c));
	IK_PRINTF("\n [0x%02X]:   0x%04x", 0x1d, afeRd (bmeNum, port, 0x1d));
	IK_PRINTF("\n [0x%02X]:   0x%04x", 0x1e, afeRd (bmeNum, port, 0x1e));
	IK_PRINTF("\n [0x%02X]:   0x%04x", 0x1f, afeRd (bmeNum, port, 0x1f));


	for (i = 1;i < 8;i++)
		IK_PRINTF("IFE Reg %02x %04x:\n", i, ifeRd (bmeNum, port, i));

	IK_PRINTF("IFE Global Regs:\n");
	IK_PRINTF("IFE Reg 0 %04x:\n",  ifeRd (bmeNum, port, 0));
	IK_PRINTF("IFE Reg 8 %04x:\n",  ifeRd (bmeNum, port, 8));
	IK_PRINTF("IFE Reg 0x10 %04x:\n",  ifeRd (bmeNum, port, 0x10));
	IK_PRINTF("IFE Reg 0x18 %04x:\n",  ifeRd (bmeNum, port, 0x18));


	dumpCoeff(bmeNum, port, 12);
}


/*
************************************************************************
	Function: IFE Read

	void ifeRd (int bmeNum, int port, int addr)
	
   Description:
		This function allows a read access to any IFE registers, Reg-0 and Reg-1
		
		Input: 
			port: 0-3
			addr; IFE register number, 0-1 for IFE2
					1..7 for ife_co5 per port
					0,8,0x10,0x18 for global
					
			
		Output:
			32 bit register value
************************************************************************
*/

int ifeRd5 (int bmeNum, int port, int addr)
{
    int cmd_val = -1; 
    int status, i;
	int portVal = 0;



	if ((ifeId [bmeNum] [port] & IFE_REV_ID_MASK ) == IFE_CPE5_DEV_ID)  
	{
		return afeRd (bmeNum, port, addr);

	}

	// 32 ife 5 registers
	if (addr < 0x20)
	{
		if ( (port >= 0) && (port < MAX_PORT_PER_BME) )
		{
			/* clear stat reg */
			afeWr (bmeNum, port, AFE_IFE_RDWR_STAT, IFE_STATUS_CLEAR);

			if ( ifeType [bmeNum] [port] == IFE_CO50_TYPE )

			{
				// see 9.22 AFE Manual, and IFE Manual Section 5
				// if its a global reg then set port to 0. the reg_addr contains the correct address. 
				// if is a port spec reg then the expected input is address  1..7 NOT higher. The port value * 8
				// will convert it to the correct address. 

				if 	( // global registers
					(addr == IFE_CO5_REV_ID) ||
					(addr == IFE_CO5_TUNER)	   ||
					(addr == IFE_CO5_BANDGAP)	 ||
					(addr == IFE_CO5_COM_MISC)	   
					)
					portVal =0;
				else
					portVal = port;
					// bits 8..9 always 0 if connected to ife co5
				cmd_val = IFE_REG_RD + (portVal * 8) + addr;
			}
			else
				cmd_val = IFE_REG_RD + (port << 8) + addr;


			afeWr (bmeNum, port, AFE_IFE_RDWR_CMD, cmd_val);

			i = 0;
			while ( 1 )
			{
	            BUP_DELAY_MS(1);
				status = afeRd (bmeNum, port, AFE_IFE_RDWR_STAT);

				if ( status & IFE_CMD_PASS )
				{
					break;
				}
		  
				if ( (++i > AFE_MAX_RW_REPEAT) || (status & IFE_CMD_FAIL) )
				{
					DBG0(("\n\t Bme %d Afe %d failed to access IFE %d reg %d %x\n",
                        bmeNum, port/NUM_PORTS_PER_AFE, port%NUM_PORTS_PER_AFE , addr, status))
					return -1;
				}
			}

			cmd_val = afeRd (bmeNum, port, AFE_IFE_REG_RD_DATA);
		}
		else
		{
			IK_PRINTF("\ninvalid port... port: %d\n", port);
		}
	}
	else
	{
		IK_PRINTF("\ninvalid IFE Registers %d (0-1)\n", addr);
	}

	//IK_PRINTF("\n read %08x reg %08x port %d\n", cmd_val, addr, port);
	return (cmd_val);
}
int ifeRd2 (int bmeNum, int port, int addr)
{
    int cmd_val = -1; 
    int status, i;

  
  	if ( (addr == IFE2_REG_0) || (addr == IFE2_REG_1) )
	{
		if ( (port >= 0) && (port < MAX_PORT_PER_BME) )
		{
			/* clear stat reg */
			afeWr (bmeNum, port, AFE_IFE_RDWR_STAT, IFE_STATUS_CLEAR);

			cmd_val = IFE_REG_RD + (port << 8) + addr;
			afeWr (bmeNum, port, AFE_IFE_RDWR_CMD, cmd_val);

			i = 0;
			while ( 1 )
			{
	            BUP_DELAY_MS(1);
				status = afeRd (bmeNum, port, AFE_IFE_RDWR_STAT);

				if ( status & IFE_CMD_PASS )
				{
					break;
				}
		  
				if ( (++i > AFE_MAX_RW_REPEAT) || (status & IFE_CMD_FAIL) )
				{
					DBG0(("\n\t Bme %d Afe %d failed to access IFE %d reg %d\n",
                        bmeNum, port/NUM_PORTS_PER_AFE, port%NUM_PORTS_PER_AFE, addr))
					return -1;
				}
			}

			cmd_val = afeRd (bmeNum, port, AFE_IFE_REG_RD_DATA);
		}
		else
		{
			IK_PRINTF("\ninvalid port... port: %d\n", port);
		}
	}
	else
	{
		IK_PRINTF("\ninvalid IFE Registers %d (0-1)\n", addr);
	}

	//IK_PRINTF("\n read %08x reg %08x port %d\n", cmd_val, addr, port);
	return (cmd_val);
}





/*
************************************************************************
	Function: IFE Write

	void ifeWr (int bmeNum, int port, int addr, data)
	
   Description:
		This function writes the given data to a IFE registers, Reg-0 and Reg-1
		
		Input: 
			port: 0-3
			addr: IFE register number, 0-1
			data:
			
		Output:
			None.
************************************************************************
*/
void ifeWr5 (int bmeNum, int port, int addr, int data)
{
 int cmd_val = -1;
 int i, status;
 int portVal;


	 if ((ifeId [bmeNum] [port] & IFE_REV_ID_MASK ) == IFE_CPE5_DEV_ID)  
	 {
		 afeWr (bmeNum, port, addr, data);
		 return;
	 }



  
	if (addr < 0x20)
	{
		if ( (port >= 0) && (port < MAX_PORT_PER_BME) )
		{
			/* clear stat reg */
			afeWr (bmeNum, port, AFE_IFE_RDWR_STAT, IFE_STATUS_CLEAR);

			/* write the data */
			afeWr (bmeNum, port, AFE_IFE_REG_WR_DATA, data);

			if ((ifeId [bmeNum] [port] & IFE_REV_ID_MASK ) == IFE_CO5)
			{
				// see 9.22 AFE Manual, and IFE Manual Section 5
				// if its a global reg then set port to 0. the reg_addr contains the correct address. 
				// if is a port spec reg then the expected input is address  1..7 NOT higher. The port value * 8
				// will convert it to the correct address. 

				if 	( // global registers dont use port number to calc the address. so set port to 0
					 (addr == IFE_CO5_REV_ID) || 
					 (addr == IFE_CO5_TUNER)	||
					 (addr == IFE_CO5_BANDGAP)	  ||
					 (addr == IFE_CO5_COM_MISC)		
					)
					portVal =0;
				else
					portVal = port;
					// bits 8..9 always 0 if connected to ife co5
				cmd_val = IFE_REG_WR + (portVal * 8) + addr;
			}
			else
				cmd_val = IFE_REG_WR + (port << 8) + addr;
			afeWr (bmeNum, port, AFE_IFE_RDWR_CMD, cmd_val);

			i = 0;
			while (1)
			{
	            BUP_DELAY_MS(1);
				status = afeRd (bmeNum, port, AFE_IFE_RDWR_STAT);
				if ( status & IFE_CMD_PASS )
				{
					break;
				}
		  
				if ( (++i > AFE_MAX_RW_REPEAT) || (status & IFE_CMD_FAIL) )
				{
					IK_PRINTF("\n\t failed to access IFE reg-%d... [%x]\n", addr, cmd_val);
					break;
				}
			}
		}
		else
		{
			IK_PRINTF("\ninvalid port... port: %d\n", port);
		}
	}
	else
	{
		IK_PRINTF("\ninvalid IFE Registers %d (0-1)\n", addr);
	}
}

void ifeWr2 (int bmeNum, int port, int addr, int data)
{
 int cmd_val = -1;
 int i, status;
  	if ( (addr == IFE2_REG_0) || (addr == IFE2_REG_1) )
	{
		if ( (port >= 0) && (port < MAX_PORT_PER_BME) )
		{
			/* clear stat reg */
			afeWr (bmeNum, port, AFE_IFE_RDWR_STAT, IFE_STATUS_CLEAR);

			/* write the data */
			afeWr (bmeNum, port, AFE_IFE_REG_WR_DATA, data);

			cmd_val = IFE_REG_WR + (port << 8) + addr;
			afeWr (bmeNum, port, AFE_IFE_RDWR_CMD, cmd_val);

			i = 0;
			while (1)
			{
	            BUP_DELAY_MS(1);
				status = afeRd (bmeNum, port, AFE_IFE_RDWR_STAT);
				if ( status & IFE_CMD_PASS )
				{
					break;
				}
		  
				if ( (++i > AFE_MAX_RW_REPEAT) || (status & IFE_CMD_FAIL) )
				{
					IK_PRINTF("\n\t failed to access IFE reg-%d... [%x]\n", addr, cmd_val);
					break;
				}
			}
		}
		else
		{
			IK_PRINTF("\ninvalid port... port: %d\n", port);
		}
	}
	else
	{
		IK_PRINTF("\ninvalid IFE Registers %d (0-1)\n", addr);
	}
}

void ifeWr (int bmeNum, int port, int addr, int data)
{
	if (ifeType[bmeNum] [port]  & 0x1)
		ifeWr5 ( bmeNum,  port,  addr,  data);
	else
		ifeWr2 ( bmeNum,  port,  addr,  data);

}
int ifeRd (int bmeNum, int port, int addr)
{
	if (ifeType[bmeNum] [port]  & 0x1)
		return ifeRd5 (bmeNum,  port,  addr);
	else
		return ifeRd2 (bmeNum,  port,  addr);

}


/*
************************************************************************
	Function: Retune IFE Device
	
	Description:
		This function retunes ife for the given port
		
	Return Value: none
************************************************************************
*/
void retuneIfe (int bmeNum, int port)
{
	if ( (port >= 0) && (port < MAX_PORT_PER_BME) )
	{
	 int iCmd, iIfeNum = 0;

   		// retune is a global register in IFE co5. 0 = ife2, else ife5
		if ((afeId [bmeNum] [port/4] == AFE_CO5)  || (afeId [bmeNum] [port/4] == AFE_CO5))
			iIfeNum = 0;
		else
			iIfeNum = ((1 << port) << 8) & SEL_IFES_MASK;
	
		iCmd =  IFE_RETUNE_ON + iIfeNum;
		afeWr (bmeNum, port, AFE_IFE_RETUNE_CTRL, iCmd);
	    BUP_DELAY_MS(1);
	
		iCmd = IFE_RETUNE_OFF + iIfeNum;
		afeWr (bmeNum, port, AFE_IFE_RETUNE_CTRL, iCmd);
	    BUP_DELAY_MS(1);
	}
	else
	{
		IK_PRINTF("\ninvalid port... port: %d\n", port);
	}
}

int inServiceTest(int bmeNum, int port)
{
	int afeNum;
	int ret0;
	int ret1;

     IK_PRINTF ("\nIn service test\n");
	afeNum = port/NUM_PORTS_PER_AFE;
	
	ret0 = chkAfeRevId (bmeNum, afeNum);
    	if (ret0 == -1)
    	{
      	IK_PRINTF("AFE Version read failed on port %d\n", port);
    	}
    	else
    	{
		IK_PRINTF("AFE Version is 0x%3x\n", ret0);
    	}

	ret1 = chkIfeRevId(bmeNum, port);
    	if (ret1 == -1)
    	{
      	IK_PRINTF("IFE Version read failed on port %d\n", port);
    	}
    	else
    	{
		IK_PRINTF("IFE Version is 0x%x\n", ret1);
    	}
	return ((ret0 != -1) && (ret1 != -1));
}

/*
************************************************************************
	Function: hldWrite
	
	Description:
		
	Return Value: none
************************************************************************
*/
//void hldWrite (int bmeNum, int hldNum, int whichPortInHLD, int data)
void hldWrite (int bmeNum, int port, int data)
{

	int hldNum; 
	int whichPortInHLD;


	// hldnum will be 0 or 1, 2 for each afe
	// whichPortInHLD = 0,1 2 for each HLD
	hldNum = (port>>1) & 1;
	whichPortInHLD	= port&1;


	// wait for done bit
	while (afeRd (bmeNum, port, AFE_HLD_REG_RD_WR_STAT) & (BIT31));

	// 11 bit data on bits 17:27. Bit 16 selects one of the 2 ports
	afeWr (bmeNum, port, AFE_HLD_REG_RD_WR_STAT, (data << 17) + (whichPortInHLD << 16));

	// write to the hld selected
	afeWr (bmeNum, port, AFE_HLD_RDWR_CMD , (hldNum&1) + (BIT30));

}


/*
************************************************************************
	Function: hldRead
	
	Description:
		
	Return Value: none
************************************************************************
*/
//int hldRead (int bmeNum, int hldNum, int whichPortInHLD)
int hldRead (int bmeNum, int port)
{

	int data;
	int hldNum; 
	int whichPortInHLD;



	// hldnum will be 0 or 1, 2 for each afe
	// whichPortInHLD = 0,1 2 for each HLD
	hldNum = (port>>1) & 1;
	whichPortInHLD	= port&1;


	// write to the hld selected
	afeWr (bmeNum, port, AFE_HLD_RDWR_CMD , (hldNum&1) + (BIT31));

	// wait for done bit
	while (afeRd (bmeNum, port, AFE_HLD_REG_RD_WR_STAT) & (BIT31));

	data =  afeRd (bmeNum, port, AFE_HLD_REG_RD_WR_STAT);
	return data&0xfff;

}





/*
************************************************************************
    Function: Clear IFE RDWR STAT Reg

    Description:
        clear ife rdwr stat register within the afe_co30 by writing '1'
        to appropriate bits

    Return Value: void
************************************************************************
*/
void clearIfeRdwrStat (int bmeNum, int port)
{
    afeWr (bmeNum, port, AFE_IFE_RDWR_STAT, IFE_STATUS_CLEAR);

}



void hld_strobe(int bmeNum, int port)
{
   //If you are inside here you must be using AFECO3 with a CO5 HLD configuration.

    int cmd;
    unsigned int ifeCs;
    int reg_addr = IFE2_REG_0;  //dummy. will never be written
    //int data = 0x5fe4bfbf;      //dummy. will never be written


    //This is needed, apparently ife status maybe busy due to access to IFE CO5. If that happens
    // the strobe signal to IFE can not be genenerated.
    clearIfeRdwrStat(bmeNum, port);   //afeWriteRegister(AFE_IFE_RDWR_STAT, port, IFE_STATUS_CLEAR);

    //--------------Remove Maybe taking too long!---------------------
    /* setup ife registers within the afe */
    //afeWriteRegister(AFE_IFE_REG_WR_DATA, port, data);  // No need! write what ever is in there
    //----------------------------------------------------------



    //cmd = IFE_REG_WR + (MAP_CHAN(port) << 8) + (reg_addr & iIfeRegMask);
    //Port 
    // 0 1  -> AFE0 IFE1 SCS
    // 2 3  -> AFE0 IFE2 SCS
    // 4 5  -> AFE1 IFE1 SCS
    // 6 7  -> AFE1 IFE2 SCS
    
    if( (MAP_CHAN(port)) > 1)
        ifeCs = 2 << 8;
    else
        ifeCs = 1 << 8;
    
    cmd = IFE_REG_RD | ifeCs | (reg_addr & iIfeRegMask);

    afeWr (bmeNum, port, AFE_IFE_RDWR_CMD, cmd);
    afeWr (bmeNum, port, AFE_IFE_RDWR_STAT, IFE_STATUS_CLEAR);
}




int hldTest(int bmeNum, int port)
{

	unsigned short int dataPattern1 = 0x1;
	unsigned short int dataPattern2 = 0x2;
	unsigned short int dataPattern3 = 0x3;
	unsigned int readPattern;
	unsigned int readPattern1 = 6;
	unsigned int readPattern2 = 0xc;
	unsigned int readPattern3 = 0xe;
	int failureNum = 0;



#ifdef CPE_50
	hldWrite(bmeNum,0, 0xaa);
	readPattern = hldRead(bmeNum, 0);
	if (readPattern != (0xaa <<1))
	{
		printf("HLD Write/read verify Failed. Read: %x Should be: 0xaa\n", readPattern);
		return ERROR;
	}
	else
	{
		printf("HLD Write/read verify Passed Port %d\n", port);
		return 0;
	}

#endif


	/*
		HLD read is broken with the AFE-CO5. It doesnt read back what u write. Its
		inverted and shifted in some way. However it IS predictable.. so im using the above
		3 data patterns:
		
			if u write 1 u get back 6
			if u write 2 u get back c
			if u write 3 u get back e
			
		to verify the HLD			
	*/






	hldWrite(bmeNum, port, dataPattern1);
	readPattern = hldRead(bmeNum, port);
	if (readPattern1 != readPattern1)
	{
		printf("HLD Write/read verify Failed Port %d. Read: %x Should be: %x\n", port, readPattern1, dataPattern1);
		return ERROR;
	}
	else
	{
		printf("HLD Write/read verify Passed Port %d\n", port);
	}
	


	hldWrite(bmeNum, port, dataPattern2);
	readPattern = hldRead(bmeNum, port);
	if (readPattern1 != readPattern2)
	{
		printf("HLD Write/read verify Failed Port %d. Read: %x Should be: %x\n", port, readPattern2, dataPattern2);
		return ERROR;
	}
	else
	{
		printf("HLD Write/read verify Passed Port %d\n", port);
	}



	hldWrite(bmeNum, port, dataPattern3);
	readPattern = hldRead(bmeNum, port);
	if (readPattern3 != readPattern)
	{
		printf("HLD Write/read verify Failed Port %d. Read: %x Should be: %x\n", port, readPattern3, dataPattern3);
		return ERROR;
	}
	else
	{
		printf("HLD Write/read verify Passed Port %d\n", port);
	}


}



#endif //CO_30








