#ifdef CO_30_DIAGS

/************** INCLUDE FILES ****************************/
#include <stdio.h>
#include <ctype.h>
#include <diags_defines.h>
#include <diags_mode.h>
#include <diags_ver.h>
#include "apposmacro.h"
#include "apitype.h"
#include "oampdb.h"
#include "bmehwapi.h"

/************** LOCAL MACROS *****************************/

// these two same as in appstart.c
#define	UI_TASK_PRIORITY            90
#define	UI_TASK_STACK_SIZE	        8192

#define UL2_GLCONF                  0xE0000000
#define UL2_STICR                   0xE0000100
#define UL2_STFCR                   0xE0000120
#define UL2_SRCR                    0xE0000200
#define UL2_SOFT_RESET              0xE0000004
#define HDE_SOFT_RESET_OFFSET       0x04

#define HDE_REGISTER_BASE_ADDR      0xE0000500
#define PL2_TX_PARITY_ERRCNT        0xE0000010  
#define HDE_TX_FRAME_COUNT_REG        0x14
#define HDE_TX_BYTES_COUNT_REG        0x18
#define HDE_TX_TERR_COUNT_REG         0x1C
#define HDE_TX_SHORT_FRAME_COUNT_REG  0x20
#define HDE_TX_LONG_FRAME_COUNT_REG   0x24
#define HDE_TX_PL2_INT_ERR_COUNT_REG  0x28
#define HDE_TX_DROP_COUNT_REG         0x2C

#define HDE_RX_FRAME_COUNT_REG        0x34
#define HDE_RX_BYTES_COUNT_REG        0x38
#define HDE_RX_TERR_COUNT_REG         0x3C
#define HDE_RX_SHORT_FRAME_COUNT_REG  0x40
#define HDE_RX_LONG_FRAME_COUNT_REG   0x44
#define HDE_RX_DROP_COUNT_REG         0x4C

#define MAX_PORTS_PER_BME           8

#define UL2_RX_FAST_CHANNEL(p)      (p*2)
#define UL2_RX_INTL_CHANNEL(p)      ((p*2) + 1)

#define CHANNEL_ENABLE              0x80000000
#define CHANNEL_DISABLE             0x00000000

#define PL2_LOOPBACK_ENABLE         0x1000

#define FAST_PATH                   1
#define INTL_PATH                   2
#define AFE_CO3             (0xb10)
#define AFE_CO5             (0xc10)


/************** GLOBAL VARIABLES *************************/
static int bup_bme = 1;
static U8 buffer [32];
int gDiagDbgLvl = 1;
int gBmeMemSz[IPOS_MAX_BME+1];
int diagsHoldCpuInReset = 0;
int diagsManualMode = 0;
extern tBmeStruct BmeStruct[];


/************** EXTERN FUNCTIONS AND VARIABLES ***********/
int HicPIOBulkRWTest (int bmeNum);
int HicDMARWTest (int bmeNum);
int HicTimeoutTest (int bmeNum);
int bup_SdramRandom (int bmeNum);
int bup_afe_reg_rw (int bmeNum);
int bup_testIfe (int bmeNum, int j);
int bup_write_read_whole_memory (int bmeNum);
int bup_memTestAddrData (int bmeNum);
int testPIORead1 (int BmeNum, unsigned long addr);
void testPIOWrite (int BmeNum, unsigned long addr, unsigned long data);
void taskUi(void);
void bmeHwResetApi (int BmeNum);
void bup_InitSdramCO (int bmeNum, int x16, int OpenPage);
void bup_SendMsgUartCO (int bmeNum, int tstUart);
int bup_LoopbackUartCO (int bmeNum, int TxUart);
int bup_SdramDma (int bmeNum, int NumBytes, UINT32 StartData, int whichDMA);
int bup_regress_dma (int bmeNum);
int bup_sdram_dma_1_100bytes (int bmeNum);
int bup_SdramFifoDma (int bmeNum);
int bup_check_bme_id (int bmeNum);
int AfeCO3test (int bmeNum, int port);
int IfeTestCO3 (int bmeNum, int port);
void bmeRelCpu (tBmeStruct *pBme,unsigned char enable);
unsigned int detectBmeMemSize (int bmeNum);
void InitSdramM (int x16, int OpenPage, int which);
void set_clkM (int which);
unsigned int getRelCpuStatus (void);
int lbist_loop (int bmeNum);
static int bup_PL2CntList();
void bup_config_phe();
int bup_all_loopback();
void bup_all_stats_phe ();
void ddr_walk_test (int bmeNum, int port );

extern int doConsoleTimeOut;
/* extern tBmeStruct  	BmeStruct[IPOS_MAX_BME+1]; */ /* BME objects for direct API */
extern int gCoreClk, gMemClk, gRefreshRate; // from sdram.c

/************** LOCAL FUNCTION PROTOTYPES ****************/
static void bup_init (int bmeNum);
static void print_diag_menu (void);
static void inputSkipBlanks(U8 **pCmd);
static int getInputValue (U8 **pCmd, int *retVal);
static void printInputError (void);
static int bup_HICtest (int bmeNum);
static int bup_EMITest (int bmeNum);
//static void bup_set_clk (int bmeNum);
//static int bup_UARTtests (int bmeNum);
static int bup_DMATest (int bmeNum);
static int bup_AFETest (int bmeNum);
static int bup_IFETest (int bmeNum);
int HIConnectionTest (int bmeNum);
static int GoToNormalMode (void);
static int changeDbgLevel (int dbgLvl);
int bup_scratch_reg_rw (int bmeNum);

int printDiagOptions (void);

void D ( int bupbme, void *adrs, int nunits, int width);
void F (int bupbme, int addr, int num, int data);


/********************************************************/
/*              LOCAL FUNCTION DEFINITIONS              */
/********************************************************/

static void print_diag_menu (void)
{
      DBG1(("\n"))
      DBG1(("NOTE: Only Test 1 will run properly before initialization.\n"))
      DBG1(("      Run 2 to initialize BME before running other tests.\n"))
      DBG1(("\n"))
      DBG1(("\tINITIALIZATION\n"))
      DBG1(("\t--------------\n"))
      DBG1(("\t  1. HIC Host-BME Connection Test\n"))
      DBG1(("\t  2. BME Core & Mem Clk, EMI Initialization\n"))
      DBG1(("\n"))
      DBG1(("\tHOST BASED TESTS\n"))
      DBG1(("\t----------------\n"))
      DBG1(("\t  11. HIC PIO SDRAM Read/Write Tests\n"))
      DBG1(("\t  12. SDRAM Address & Data Bus Connection Tests\n"))
      DBG1(("\t  13. Walking 1s & 0s Full SDRAM Read/Write Test\n"))
      DBG1(("\t  14. Memory to Memory BME DMA Tests\n"))
      DBG1(("\t  15. BME-AFE DDR Bus Connection Tests\n"))
      DBG1(("\t  16. AFE/IFE Register Read/Write Tests\n"))
#ifndef CPE_50
      DBG1(("\t  17. PL2 Loop back Tests (per port)\n"))
      DBG1(("\t  18. PL2 Counters List (all ports)\n"))
      DBG1(("\t  19. PL2 Counters List (per channel)\n"))
#endif
      DBG1(("\t  20. BME-AFE DDR Bus Walk Tests\n"))


      DBG1(("\n"))
      DBG1(("\tDEBUG UTILITIES\n"))
      DBG1(("\t---------------\n"))
      DBG1(("\t  21. HIC PIO Read  => 21 <addr> <num_32bit_words>\n"))
      DBG1(("\t  22. HIC PIO Write => 22 <addr> <num_32bit_words> <32bit_data>\n"))
#ifndef CPE_50
      DBG1(("\t  23. Set BME core and memory clock parameters\n"))
#endif
      DBG1(("\t  24. Detect Memory Size [0x%x]\n", gBmeMemSz[bup_bme]))
      DBG1(("\n"))
      DBG1(("\tDIAGS OPTIONS\n"))
      DBG1(("\t-------------\n"))
      DBG1(("\t  31. Change diags power-on option\n"))
      DBG1(("\t  32. Change BME number [%d] => 32 <bme_num>\n", bup_bme))
      DBG1(("\t  33. Change diag debug level [%d] => 33 <dbgLvl>\n", gDiagDbgLvl))
      DBG1(("\n"))
      DBG1(("\tBRINGUP UTILITIES\n"))
      DBG1(("\t-----------------\n"))
      DBG1(("\t  61. Download code and start BME\n"))
      DBG1(("\t  62. Download code without launching host application\n"))
      DBG1(("\t  63. Download code without releasing Xtensa CPU\n"))
      DBG1(("\t  64. Release Xtensa CPU\n"))
      DBG1(("\n*****************************************************\n"))  
}

static void bup_init (int bmeNum)
{

	  iposTaskDelay (10);
	  bmeHwResetApi (bmeNum);
      iposTaskDelay (10);
//	  bup_InitSdramCO (bmeNum, 1,1);
      DBG1(("Bme %d: Initializing external memory interface\n", bmeNum))
      InitSdramM (1,1,bmeNum);
//	  bup_set_clk (bmeNum);
      DBG1(("Bme %d: Initializing BME core and memory clocks\n", bmeNum))
#ifndef CPE_50
      set_clkM(bmeNum);
#endif
      iposTaskDelay (10);
      DBG1(("BME %d INITIALIZED\n", bmeNum))
}

#if 0
static void bup_set_clk (int bmeNum) {
    // Core PLL Control Register
    testPIOWrite (bmeNum, CKM_PCR(0),           (0x11<<2) | 0x3); // 148.50MHz
    testPIOWrite (bmeNum, CKM_PCR(0),  (1<<8) | (0x11<<2) | 0x3); // PLL counter reset
    // Memory PLL Control Register
    testPIOWrite (bmeNum, CKM_MPCR(0),          (0x10<<2) | 0x3); // 140 MHz
    testPIOWrite (bmeNum, CKM_MPCR(0), (1<<8) | (0x10<<2) | 0x3); // PLL counter reset
}
#endif

// skip blanks by advancing the string pointer
static void inputSkipBlanks(U8 **pCmd)
{
    while( ((U8)(*(*pCmd))) == ' ') 
        (*pCmd)++ ; 
}

// This function takes the input string and
// extracts the arguments. Returns 1 if arg
// is available. Returns 0 is string is null.
static int getInputValue (U8 **pCmd, int *retVal)
{
    inputSkipBlanks (pCmd);
    if ( ((U8)(*(*pCmd))) == '\0' )
        return 0;
    *retVal = strtoul ((char *)*pCmd, (char **)pCmd, 0);
    return 1;
}

static void printInputError (void)
{
    DBG1(("Insufficient input parameters\n"))
}

int HIConnectionTest (int bmeNum)
{
    int error = 0;
    error =  bup_scratch_reg_rw (bmeNum);
	error |= bup_check_bme_id (bmeNum);
    
    if (error == -1)
    {
        DBG0(("**** HIC CONNECTION TEST FAILED ****\n"));
    }
    else
    {
        DBG1(("HIC CONNECTION TEST PASSED\n"));
    }
    return error;
}
static int bup_HICtest (int bmeNum)
{
    UINT32 data = 0, data1 = 0;
    int retVal;

    /* do two single HIC PIO write & read */
	testPIOWrite (bmeNum, HIC_PIO_TEST_MEM_ADDR, 0xFEDC0123);
	data = testPIORead1 (bmeNum, HIC_PIO_TEST_MEM_ADDR);
	testPIOWrite (bmeNum, HIC_PIO_TEST_MEM_ADDR, 0x765489AB);
	data1 = testPIORead1 (bmeNum, HIC_PIO_TEST_MEM_ADDR);

    if ((data == 0xFEDC0123) && (data1 == 0x765489AB))
        DBG1(("Bme %d: Single HIC PIO Read/Write test passed\n", bmeNum))
    else
    {
        DBG0(("Single HIC PIO Read/Write test FAILED\n"))
        DBG0(("**** HIC PIO SDRAM R/W TEST FAILED ****\n"))
        return -1;
    }

    if ((retVal = HicPIOBulkRWTest (bmeNum)) != 0)
    {
        DBG0(("**** HIC PIO SDRAM R/W TEST FAILED ****\n"))
        return retVal;
    }
#ifdef CO_20
    if ((retVal = HicDMARWTest (bmeNum)) != 0)
    {
        DBG0(("**** HIC PIO SDRAM R/W TEST FAILED ****\n"))
        return retVal;
    }
#endif
#if 0
    if ((retVal = HicTimeoutTest (bmeNum)) != 0)
    {
        DBG0(("HIC TEST FAILED\n"))
        return retVal;
    }
#endif

    DBG1(("HIC PIO SDRAM R/W TEST PASSED\n"))
    return 0;
}


static int bup_EMITest (int bmeNum)
{
    int retVal;
    DBG1(("Bme %d: External memory interface test\n", bmeNum))
	retVal = bup_SdramRandom (bmeNum);

    if (retVal != 0)
        DBG0(("**** EMI TEST FAILED ****\n"))
    else
        DBG1(("EMI TEST PASSED\n"))

    bup_init (bup_bme);
	//bup_InitSdramCO (bmeNum, 1,1);

    return retVal;
}

#ifndef CPE_50
void setclockOptions (void)
{
    unsigned int coreclk;
    unsigned int memclk;
    unsigned int refresh;
    DBG1(("\nFor the changes to take effect, run 2 after the settings.\n"))
    DBG1(("Current values are: core clk 0x%x, mem clk 0x%x, refresh 0x%x.\n\n",
                gCoreClk, gMemClk, gRefreshRate))
    DBG1(("0x6 - 52.5MHz    0x7 - 61.25MHz    0x8  - 70MHz    0x9  - 78.5MHz\n"))
    DBG1(("0xA - 87.5MHz    0xB - 96.25MHz    0xC  - 105MHz   0xD  - 113.75MHz\n"))
    DBG1(("0xE - 122.5MHz   0xF - 131.25MHz   0x10 - 140MHz   0x11 - 148.5MHz\n"))
    DBG1(("\nEnter one of the above options for core clock frequency: "))
    scanf ("%x", &coreclk);
    if (coreclk < 0x6 || coreclk > 0x11)
    {
        DBG1(("Incorrect value.\n"))
        gets(buffer); //to clear input
        return;
    }
    else
    {
        gCoreClk = coreclk;
    }
    DBG1(("Enter one of the above options (max 0x10) for memory clock frequency: "))
    scanf ("%x", &memclk);
    if (memclk < 0x6 || memclk > 0x10)
    {
        DBG1(("Incorrect value.\n"))
        gets(buffer); //to clear input
        return;
    }
    else
    {
        gMemClk = memclk;
    }
    refresh = ((50 + ((coreclk - 6) * 9)) * 15) - 20; //approximated from cobra prog. manual
    DBG1(("Enter the memory refresh period in core clock cycles (approx 0x%x): ", refresh))
    scanf ("%x", &refresh);

    gRefreshRate = refresh;

    gets(buffer); //to clear input
    return;
}
#endif

static int bup_AFETest (int bmeNum)
{
    int error = 0;

    DBG1(("\nBme %d AFE register read/write tests:\n", bmeNum))
#ifdef CO_20
	error = bup_afe_reg_rw (bmeNum);



#elif defined(CO_30) || defined(CO_30_DIAGS)
#ifndef CO_30_EMULATION
	error = AfeCO5test (bmeNum, 0);
	if (!error)
    {
        DBG1(("AFE 0 TEST PASSED"))
    } else {
        DBG0(("**** AFE 0 TEST FAILED ****"))
    }
    DBG1(("\n"))

	error = AfeCO5test (bmeNum, 1);
	if (!error)
    {
        DBG1(("AFE 1 TEST PASSED"))
    } else {
        DBG0(("**** AFE 1 TEST FAILED ****"))
    }
    DBG1(("\n"))

#else
    DBG1(("AFE not available on emulation board\n"));
    return 0;
#endif //CO_30_EMULATION
#endif //elif defined(CO_30)

	return error;
}

//int Mport = 1;

static int bup_IFETest (int bmeNum)
{
int port = 0;
int error = 0;
int ret;
#define IFE_CO50_TYPE           (0x01)


    DBG1(("\n\nBme %d IFE register read/write tests:\n", bmeNum))
	for (port = 0;port < IPOS_MAX_PORT_PER_BME; port++)
    {
#ifdef CO_20
		error |= bup_testIfe (bmeNum, port);
#elif defined(CO_30)
#ifndef CO_30_EMULATION
		error |= IfeTestCO5 (bmeNum, port);
#else
        DBG1(("IFE not available on emulation board\n"));
        return 0;
#endif //CO_30_EMULATION
#endif //elif defined(CO_30)
    }

	return error;
}






static int bup_IFE_CPE5_Test (int bmeNum)
{
	#define AFE_BAND_GAP_CTRL	    (0x03)		// PER ch
    int error = 0;

    DBG1(("\nIFE-CPE5 register read/write tests:\n", bmeNum))

	// bug work around
	afeWr (bmeNum, 0, AFE_BAND_GAP_CTRL, 0);


	error = AfeCO5test (bmeNum, 0);
	error |= IfeTestCO5 (bmeNum, 0);
	if (!error)
    {
        DBG1(("IFE-CPE5 TEST PASSED"))
    } else {
        DBG0(("**** IFE-CPE5 TEST FAILED ****"))
    }

	return error;
}








/*
static int bup_UARTtests (int bmeNum)
{
    int error;
	bup_SendMsgUartCO (bmeNum, 0); 
	bup_SendMsgUartCO (bmeNum, 1); 
	error = bup_LoopbackUartCO (bmeNum, 0);
	error |= bup_LoopbackUartCO (bmeNum, 1);
	return error;
}
*/

static int bup_DMATest (int bmeNum)
{
    int error = 0;
    int numBytesToTransfer, startDataValue, dmaChannel;

    numBytesToTransfer = 1000;   // some large number
    startDataValue = 0x1a2b3c4d; // some randome value
    dmaChannel = 0;              // bme dma channel 0
	DBG1(("Bme %d: DMA Test 1 ... ", bmeNum))
	error |= bup_SdramDma (bmeNum, numBytesToTransfer, startDataValue, dmaChannel); 
	if (error)
		DBG0(("\t**** DMA Test 1 FAILED\n"))
	else
		DBG1(("Passed\n"))
	DBG1(("Bme %d: DMA Test 2 ... ", bmeNum))
	error |= bup_regress_dma (bmeNum); 
	if (error)
		DBG0(("\t**** DMA Test 2 FAILED\n"))
	else
		DBG1(("Passed\n"))

	DBG1(("Bme %d: DMA Test 3 ... ", bmeNum))
	error |= bup_sdram_dma_1_100bytes (bmeNum); 
	if (error)
		DBG0(("\t**** DMA Test 3 FAILED\n"))
	else
		DBG1(("Passed\n"))

	DBG1(("Bme %d: DMA Test 4 ... ", bmeNum))
	error |= bup_SdramFifoDma (bmeNum);
	if (error)
		DBG0(("\t**** DMA Test 4 FAILED\n"))
	else
		DBG1(("Passed\n"))

	if (error)
	{
		DBG0(("**** DMA TEST FAILED ****\n"))
	}
	else
	{
		DBG1(("DMA TEST PASSED\n"))
	}

	return error;

}

static int GoToNormalMode (void)
{
    // download bme code and start UI
    if (iposTaskSpawn("tUiTask", UI_TASK_PRIORITY, UI_TASK_STACK_SIZE,
                (taskFunc)taskUi, 0, 0, 0) == OS_ERROR)
    {
        DBG0(("Failed to start UI Task\n"))
        return -1;
    }

    // suspend the diags ui task (current task, that's why 0 tid)
    taskSuspend (0);
    return 0;
} 

int changeDbgLevel (int dbgLvl)
{
    if (dbgLvl > MAX_DBG_LVL || dbgLvl < 0)
    {
        DBG0(("debug level out of range\n"))
        return -1;
    }
    gDiagDbgLvl = dbgLvl;
    return 0;
}


/********************************************************/
/*            EXPORTED FUNCTION DEFINITIONS             */
/********************************************************/

void bup_diags (void)
{
    int uiCmd, x1, x2, x3;
    U8 *pCmd;

    // fill up the memsize array with the default value
    // It gets updated when the memory size is detected
    {
        int bmeIdx;
        for (bmeIdx = 0; bmeIdx <= IPOS_MAX_BME; bmeIdx++)
            gBmeMemSz[bmeIdx] = BME_SDRAM_MEMSIZE_BYTES_DEFAULT;
    }

    // to make sure that the BME is in hold state to run the host based tests
      if (getRelCpuStatus()) // returns 1 if BME running, 0 if BME in hold
      {
          DBG0(("BME 1 IS IN RUNNING STATE. FOR DIAGS TO EXECUTE CORRECTLY,\n"))
          DBG0(("IT HAS TO BE PUT INTO HOLD STATE BY MAKING THE RELCPU PIN HIGH.\n"))
          while (1);
      }

      //commented bup_init here, to allow manual initialization
	  //bup_init (bup_bme);
      if ((oampGetDiagsOption != BUP_DIAGS_MANUAL_MODE) &&
          (oampGetDiagsOption != BUP_DIAGS_POST_MODE) &&
          (oampGetDiagsOption != BUP_DIAGS_SKIP_MODE))
      {
          DBG1(("\nNOTE: Diags option is not set.\n"))
          DBG1(("      See the diags options menu and set as required.\n"))
      }

      // If option is set in flash, run all tests on BME1 and boot up
      // if tests pass. If any test fails, abort POST and go to manual diags
      if (!diagsManualMode && oampGetDiagsOption == BUP_DIAGS_POST_MODE)
      {
          int oldDbgLvl = gDiagDbgLvl;
          int error = 0;

          changeDbgLevel (0); // Silent POST; only errors (level 0 debugs) will be printed
          DBG0(("\nRUNNING Power On Self Test\n"))

#ifdef CO_30_EMULATION
          // This is required to give some delay before accessing BME
          // Exact reason is unknown. Problem faced on emulation board
          // wherein the diags POST hangs is the bootup delay (the
          // countdown before "load vxWorks.bdx!launch") is less than
          // 5 seconds. If the delay is 5 seconds or more, or if the
          // load is done manually, this delay here is not required.
          BUP_DELAY_MS(2000);
#endif

          error = HIConnectionTest (bup_bme);
          if (!error)
	          bup_init (bup_bme);
          if (!error)
              error = bup_HICtest (bup_bme);
          if (!error)
              error = bup_memTestAddrData (bup_bme);
          if (!error)
              error = bup_DMATest (bup_bme);
          if (!error)
              error = bup_EMITest (bup_bme);
          if (!error)
              error = lbist_loop (bup_bme);
          if (!error)
              error = bup_AFETest (bup_bme);
          if (!error)
              error = bup_IFETest (bup_bme);
          //if (!error)
              //error = bup_UARTtests (bup_bme);

          changeDbgLevel (oldDbgLvl);

          if (!error)
              error = GoToNormalMode ();
      }

    IK_PRINTF ("\n**********************************************************");
    IK_PRINTF ("\n**               Copyright (C) 2000-2002                **");
    IK_PRINTF ("\n**          Ikanos Communication, Fremont, CA           **");
    IK_PRINTF ("\n**                All rights reserved.                  **");
    IK_PRINTF ("\n**                                                      **");
    IK_PRINTF ("\n**             Bring Up Diags %s              **", bup_version);
    IK_PRINTF ("\n**********************************************************\n\n");

    print_diag_menu ();

      // to prevent doing console timeout in manual diags
      doConsoleTimeOut = 0;

	  while (1)
	  {
          DBG1(("\nEnter the diag number with arguments (0 to display the menu): "))
          gets (buffer);
          pCmd = buffer;

          if ( ! getInputValue (&pCmd, &uiCmd) )
              continue;

          switch (uiCmd)
          {
                case 0: print_diag_menu ();
                        break;
                case 1: HIConnectionTest (bup_bme);
                        break;
                case 2: bup_init (bup_bme);
                        break;
                case 11: bup_HICtest (bup_bme);
                        break;
                case 12: bup_memTestAddrData (bup_bme);
                        break;
                case 13: bup_write_read_whole_memory (bup_bme);
                        break;
                case 14: bup_DMATest (bup_bme);
                        break;
#if 0
                case 15: bup_EMITest (bup_bme); /* removed as per Vittal's */
                        break;                  /* suggestion              */
#endif
                case 15: lbist_loop (bup_bme);
                        break;
				case 16:
					 #ifdef CPE_50
						bup_IFE_CPE5_Test (bup_bme);
					 #else
						bup_AFETest (bup_bme);
                        bup_IFETest (bup_bme);
					 #endif
                        break;
					 case 17:
                        bup_config_phe();
#if !defined (CO_50) && !defined (CPE_50)
                        bup_all_loopback();
#endif
					 break;
					 case 18:
                        bup_all_stats_phe (); 
					 break;
                case 19:
                        bup_PL2CntList();
                        break;
		  case 20: 
#ifndef CPE_50
								if ( ! getInputValue (&pCmd, &x1) ) 
									 x1 = -1;
								ddr_walk_test (bup_bme, x1 );
#else
								ddr_walk_test (bup_bme, 0 );
#endif
                     	break;
#if 0
                case 5: bup_UARTtests (bup_bme); // not implemented
                        break;
#endif

                case 21: 
                        if ( ! getInputValue (&pCmd, &x1) ) { printInputError (); break; }
                        if ( ! getInputValue (&pCmd, &x2) ) { printInputError (); break; }

                        //if ((x1 >= BME_SDRAM_MEMBASE) && (x1 < BME_SDRAM_MEMBASE + gBmeMemSz[bup_bme]))
                            D (bup_bme, (void *)x1, x2, 4);
                        //else
                        //    DBG1(("address %08x out of range\n",x1))
                        break;
                case 22: 
                        if ( ! getInputValue (&pCmd, &x1) ) { printInputError (); break; } // address
                        if ( ! getInputValue (&pCmd, &x2) ) { printInputError (); break; } // number of locations to fill
                        if ( ! getInputValue (&pCmd, &x3) ) { printInputError (); break; } // 32 bit data to fill

                        //if ((x1 >= BME_SDRAM_MEMBASE) && (x1 < BME_SDRAM_MEMBASE + gBmeMemSz[bup_bme]))
                            F (bup_bme, x1,x2,x3);
                        //else
                        //    DBG1(("address %08x out of range\n",x1))
                        break;
#ifndef CPE_50
                case 23:
                         setclockOptions ();
                         break;
#endif
                case 24: 
                        detectBmeMemSize (bup_bme);
                        DBG1(("Bme external memory size is 0x%x bytes (%d megabytes)\n",
                                    gBmeMemSz[bup_bme], gBmeMemSz[bup_bme]/0x100000))
                        break;
#if 0
// redundant as 21 & 22 are there
              case 23: 
                    {
                        UINT32 regVal;
                        if ( ! getInputValue (&pCmd, &x1) ) { printInputError (); break; }
                        regVal = testPIORead1 (bup_bme, (UINT32) x1);
                        DBG1(("reg = 0x%8x data = 0x%8lx\n", x1, regVal))
                    }
                        break;
                case 24: 
                        if ( ! getInputValue (&pCmd, &x1) ) { printInputError (); break; }
                        if ( ! getInputValue (&pCmd, &x2) ) { printInputError (); break; }

                        testPIOWrite (bup_bme, (UINT32) x1, (UINT32) x2);
                        break;
#endif

                case 31:
                        printDiagOptions ();
                        break;

                case 32:
                        if ( ! getInputValue (&pCmd, &x1) ) { printInputError (); break; }
                        if (x1 > IPOS_MAX_BME || x1 <= 0)
                        {
                            DBG1(("BME number out of range\n"))
                            break;
                        }
                        bup_bme = x1;
	                    bup_init (bup_bme);
                        DBG1(("Further tests will be run on BME %d\n", bup_bme))
                        break;
                case 33:
                        if ( ! getInputValue (&pCmd, &x1) ) { printInputError (); break; }
                        changeDbgLevel (x1);
                        break;

#if 0
                case 60:
                        diag_start();
                        break;
                case 70:
                        dbgIniMenu();
                        break;
#endif
                case 61:
                        GoToNormalMode ();
                        break;

                case 62:
                        bmeDnldProcedure (&BmeStruct[bup_bme]);
                        IK_PRINTF ("\n\n");
                        break;

                case 63:
                        diagsHoldCpuInReset = 1; 
                        bmeDnldProcedure (&BmeStruct[bup_bme]);
                        IK_PRINTF ("\n\n");
                        break;

                case 64:
                        bmeRelCpu (&BmeStruct[bup_bme],TRUE);   /*release BME cpu */
                        break;
                default:
                        DBG1 (("Wrong diag number!\n"))
                        break;
            }
      }
}

// this is an exported function coz it is also called in uitask.c
int printDiagOptions (void)
{
    int diagOption;

    DBG1 (("\tNext time the CO is rebooted,\n"))
    DBG1 (("\t1. Go to diags menu to run host-based tests\n"))
    DBG1 (("\t2. Run diags as POST and go to normal operation if all tests pass\n"))
    DBG1 (("\t3. Skip diags and go directly to normal operation\n\n"))

    DBG1 (("Enter the diag mode option [%d]: ", oampGetDiagsOption))
    scanf ("%d", &diagOption);
    gets (buffer); // to flush the stdio

    if (diagOption < 1 || diagOption > 3)
    {
        DBG1 (("Invalid option\n"))
        return -1;
    }

    oampSetDiagsOption( diagOption );
    return 0;
}

#if 0

#define MAX_BYTES_PER_LINE       16

#define MAXLINE         80  /* max line length for input to 'm' routine */
#define MAX_DSP_TASKS   500 /* max tasks that can be displayed */
#define MAX_DATE_STRING 21  /* dates have 21 characters */
void D 
    (
    int bupbme,
    void *adrs,    /* address to display (if 0, display next block */
    int nunits,     /* number of units to print (if 0, use default) */
    int width       /* width of displaying unit (1, 2, 4, 8) */
    )
    {
    static dNitems = 0x40;  /* default number of item to display */
    static dWidth  = 4;     /* default width */
    static void *last_adrs = 0; /* last location displayed */

    int item;      /* item counter displayed per line */
    char ascii [MAX_BYTES_PER_LINE + 1]; /* ascii buffer for displaying */
    int ix;         /* temporary count */
    UINT8 byte;     /* byte pointer for filling ascii buffer */
    UINT32 tmpLong;      /* temporary long word pointer */

    ascii [MAX_BYTES_PER_LINE] = EOS;   /* put an EOS on the string */

    if (nunits == 0)
    nunits = dNitems;   /* no count specified: use default count */
    else
    dNitems = nunits;   /* change default count */

    width = dWidth;

    if (adrs == 0)      /* no address specified: use last address */
        adrs = last_adrs;
    else
        last_adrs = adrs;

    /* round address down to appropriate boundary */

    last_adrs = (void *)((int) last_adrs & ~(width - 1));

    /* print leading spaces on first line */

    memset (ascii, '.', 16);

    IK_PRINTF ("%08x:  ", (int) last_adrs & ~0xf);

    for (item = 0; item < ((int) last_adrs & 0xf) / width; item++)
    {
    IK_PRINTF ("%*s ", 2*width, " ");
    memset (&ascii[item * width], ' ', 2*width);
    }

    /* print out all the words */

    while (nunits-- > 0)
    {
    if (item == MAX_BYTES_PER_LINE/width)
        {
        /* end of line:
         *   print out ascii format values and address of next line */

        IK_PRINTF ("  *%16s*\n%08x:  ", ascii, (unsigned int) last_adrs);
        memset (ascii, '.', MAX_BYTES_PER_LINE); /* clear out ascii buffer */
        item = 0;               /* reset word count */
        }
        tmpLong = testPIORead1 (bupbme,(UINT32)last_adrs);
        IK_PRINTF ("%08lx", (UINT32)tmpLong);
        IK_PRINTF (" ");   /* space between words */

    /* set ascii buffer */

        for (ix = 0; ix < width; ix ++)
        {
            byte = (tmpLong >> (ix*4)) & 0xff;
            if (byte == ' ' || (isascii (byte) && isprint (byte)))
            {
                ascii[item*width +3-ix] = byte;
            }
        }

    last_adrs = (void *)((int)last_adrs + width);
    item++;
    }

    /* print remainder of last line */

//    for (; item < MAX_BYTES_PER_LINE/width; item++)
//      IK_PRINTF ("%*s ", 2*width, " ");

//    IK_PRINTF ("  *%16s*\n", ascii); /* print out ascii format values */
        IK_PRINTF("\n");
    }



#endif
void F (int bupbme, int addr, int num, int data)
{
int i;
    for (i = 0;i < num*4;i+=4)
        testPIOWrite (bupbme,addr+i, data);

}


//void set_co5_lpbk()
#if defined CO_50 || defined CPE_50
void bup_config_phe()
{

    //PHE Global
    testPIOWrite(1,0xe0040000 , 0x00ff5555);
    testPIOWrite(1,0xf0040000 , 0x00ff5555);
    testPIOWrite(1,0xe0040014 , 0x00000000);

    //PHE Ch #0
    testPIOWrite(1,0xe0040500 , 0x00000311);
    testPIOWrite(1,0xe0040508 , 0xff03ff03);
    testPIOWrite(1,0xe004050c , 0x0000000c);
    testPIOWrite(1,0xe0040510 , 0x05ee003c);
    testPIOWrite(1,0xe0040554 , 0x00000001);
    testPIOWrite(1,0xe0040558 , 0x01ff0000);
    testPIOWrite(1,0xe004055c , 0x01ff0000);
    testPIOWrite(1,0xe0040560 , 0x00430000);
    testPIOWrite(1,0xe0040564 , 0x00430000);
    testPIOWrite(1,0xe0040570 , 0x3fff3fff);
    testPIOWrite(1,0xe004057c , 0x00000404);

    //PHE Ch #4
    testPIOWrite(1,0xe0040900 , 0x00000311);
    testPIOWrite(1,0xe0040908 , 0xff03ff03);
    testPIOWrite(1,0xe004090c , 0x0000000c);
    testPIOWrite(1,0xe0040910 , 0x05ee0040);
    testPIOWrite(1,0xe0040954 , 0x00000001);
    testPIOWrite(1,0xe0040958 , 0x03ff0200);
    testPIOWrite(1,0xe004095c , 0x03ff0200);
    testPIOWrite(1,0xe0040960 , 0x00cb0088);
    testPIOWrite(1,0xe0040964 , 0x00cb0088);
    testPIOWrite(1,0xe0040970 , 0x3fff3fff);
    testPIOWrite(1,0xe004097c , 0x00000404);

    //PHE Ch #8

    testPIOWrite(1,0xe0040d00 , 0x00000311);
    testPIOWrite(1,0xe0040d08 , 0xff03ff03);
    testPIOWrite(1,0xe0040d0c , 0x0000000c);
    testPIOWrite(1,0xe0040d10 , 0x05ee0040);
    testPIOWrite(1,0xe0040d54 , 0x00000101);
    testPIOWrite(1,0xe0040d58 , 0x05ff0400);
    testPIOWrite(1,0xe0040d5c , 0x05ff0400);
    testPIOWrite(1,0xe0040d60 , 0x010f00cc);
    testPIOWrite(1,0xe0040d64 , 0x010f00cc);
    testPIOWrite(1,0xe0040d70 , 0x3fff3fff);
    testPIOWrite(1,0xe0040d7c , 0x00000404);

    //PHE Ch#12
    testPIOWrite(1,0xe0041100 , 0x00000311);
    testPIOWrite(1,0xe0041108 , 0xff03ff03);
    testPIOWrite(1,0xe004110c , 0x0000000c);
    testPIOWrite(1,0xe0041110 , 0x05ee003c);
    testPIOWrite(1,0xe0041154 , 0x00000101);
    testPIOWrite(1,0xe0041158 , 0x07ff0600);
    testPIOWrite(1,0xe004115c , 0x07ff0600);
    testPIOWrite(1,0xe0041160 , 0x01530110);
    testPIOWrite(1,0xe0041164 , 0x01530110);
    testPIOWrite(1,0xe0041170 , 0x3fff3fff);
    testPIOWrite(1,0xe004117c , 0x00000404);


    //PHE Ch #0
    testPIOWrite(1,0xf0040500 , 0x00000311);
    testPIOWrite(1,0xf0040508 , 0xff03ff03);
    testPIOWrite(1,0xf004050c , 0x0000000c);
    testPIOWrite(1,0xf0040510 , 0x05ee003c);
    testPIOWrite(1,0xf0040554 , 0x00000001);
    testPIOWrite(1,0xf0040558 , 0x01ff0000);
    testPIOWrite(1,0xf004055c , 0x01ff0000);
    testPIOWrite(1,0xf0040560 , 0x00430000);
    testPIOWrite(1,0xf0040564 , 0x00430000);
    testPIOWrite(1,0xf0040570 , 0x3fff3fff);
    testPIOWrite(1,0xf004057c , 0x00000404);

    //PHE Ch #4
    testPIOWrite(1,0xf0040900 , 0x00000311);
    testPIOWrite(1,0xf0040908 , 0xff03ff03);
    testPIOWrite(1,0xf004090c , 0x0000000c);
    testPIOWrite(1,0xf0040910 , 0x05ee0040);
    testPIOWrite(1,0xf0040954 , 0x00000001);
    testPIOWrite(1,0xf0040958 , 0x03ff0200);
    testPIOWrite(1,0xf004095c , 0x03ff0200);
    testPIOWrite(1,0xf0040960 , 0x00cb0088);
    testPIOWrite(1,0xf0040964 , 0x00cb0088);
    testPIOWrite(1,0xf0040970 , 0x3fff3fff);
    testPIOWrite(1,0xf004097c , 0x00000404);

    //PHE Ch #8

    testPIOWrite(1,0xf0040d00 , 0x00000311);
    testPIOWrite(1,0xf0040d08 , 0xff03ff03);
    testPIOWrite(1,0xf0040d0c , 0x0000000c);
    testPIOWrite(1,0xf0040d10 , 0x05ee0040);
    testPIOWrite(1,0xf0040d54 , 0x00000101);
    testPIOWrite(1,0xf0040d58 , 0x05ff0400);
    testPIOWrite(1,0xf0040d5c , 0x05ff0400);
    testPIOWrite(1,0xf0040d60 , 0x010f00cc);
    testPIOWrite(1,0xf0040d64 , 0x010f00cc);
    testPIOWrite(1,0xf0040d70 , 0x3fff3fff);
    testPIOWrite(1,0xf0040d7c , 0x00000404);

    //PHE Ch#12
    testPIOWrite(1,0xf0041100 , 0x00000311);
    testPIOWrite(1,0xf0041108 , 0xff03ff03);
    testPIOWrite(1,0xf004110c , 0x0000000c);
    testPIOWrite(1,0xf0041110 , 0x05ee003c);
    testPIOWrite(1,0xf0041154 , 0x00000101);
    testPIOWrite(1,0xf0041158 , 0x07ff0600);
    testPIOWrite(1,0xf004115c , 0x07ff0600);
    testPIOWrite(1,0xf0041160 , 0x01530110);
    testPIOWrite(1,0xf0041164 , 0x01530110);
    testPIOWrite(1,0xf0041170 , 0x3fff3fff);
    testPIOWrite(1,0xf004117c , 0x00000404);


    //Enable EIU Ch
    testPIOWrite(1,0xe0098898 , 0x00000000);
    testPIOWrite(1,0xe00988c8 , 0x00000040);
    testPIOWrite(1,0xe00988cc , 0x00000600);
    testPIOWrite(1,0xe0098880 , 0x00000701);
    testPIOWrite(1,0xe0098880 , 0x00000303);
    //Enable EIU Ch
    testPIOWrite(1,0xe0099898 , 0x00000000);
    testPIOWrite(1,0xe00998c8 , 0x00000040);
    testPIOWrite(1,0xe00998cc , 0x00000600);
    testPIOWrite(1,0xe0099880 , 0x00000701);
    testPIOWrite(1,0xe0099880 , 0x00000303);
    //Enable EIU Ch
    testPIOWrite(1,0xe009a898 , 0x00000000);
    testPIOWrite(1,0xe009a8c8 , 0x00000040);
    testPIOWrite(1,0xe009a8cc , 0x00000600);
    testPIOWrite(1,0xe009a880 , 0x00000701);
    testPIOWrite(1,0xe009a880 , 0x00000303);
    //Enable EIU Ch
    testPIOWrite(1,0xe009b898 , 0x00000000);
    testPIOWrite(1,0xe009b8c8 , 0x00000040);
    testPIOWrite(1,0xe009b8cc , 0x00000600);
    testPIOWrite(1,0xe009b880 , 0x00000701);
    testPIOWrite(1,0xe009b880 , 0x00000303);

    testPIOWrite(1,0xe009c898 , 0x00000000);
    testPIOWrite(1,0xe009c8c8 , 0x00000040);
    testPIOWrite(1,0xe009c8cc , 0x00000600);
    testPIOWrite(1,0xe009c880 , 0x00000701);
    testPIOWrite(1,0xe009c880 , 0x00000303);
    //Enable EIU Ch
    testPIOWrite(1,0xe009d898 , 0x00000000);
    testPIOWrite(1,0xe009d8c8 , 0x00000040);
    testPIOWrite(1,0xe009d8cc , 0x00000600);
    testPIOWrite(1,0xe009d880 , 0x00000701);
    testPIOWrite(1,0xe009d880 , 0x00000303);
    //Enable EIU Ch
    testPIOWrite(1,0xe009e898 , 0x00000000);
    testPIOWrite(1,0xe009e8c8 , 0x00000040);
    testPIOWrite(1,0xe009e8cc , 0x00000600);
    testPIOWrite(1,0xe009e880 , 0x00000701);
    testPIOWrite(1,0xe009e880 , 0x00000303);
    //Enable EIU Ch
    testPIOWrite(1,0xe009f898 , 0x00000000);
    testPIOWrite(1,0xe009f8c8 , 0x00000040);
    testPIOWrite(1,0xe009f8cc , 0x00000600);
    testPIOWrite(1,0xe009f880 , 0x00000701);
    testPIOWrite(1,0xe009f880 , 0x00000303);




}

#elif defined CO_40

void bup_config_phe()
{

	  testPIOWrite(1, 0xe0000000, 0x00000000); // set to 16 bit mode (bit 1), clavenbcntl (bit 3)
      
      testPIOWrite(1, 0xe0040800, 0x80000000);  // XFI, quad 0 ptm mode

      testPIOWrite(1, 0xe0040100, 0x00000000);  // XFI, quad 0 fast0, init pointers
      testPIOWrite(1, 0xe0040000, 0x00000001);  // XFI, quad 0 fast0
      testPIOWrite(1, 0xe0040104, 0x00000000);  // XFI, quad 0 fast1, init pointers
      testPIOWrite(1, 0xe0040004, 0x00000801);  // XFI, quad 0 fast1
      testPIOWrite(1, 0xe0040108, 0x00000000);  // XFI, quad 0 fast2, init pointers
      testPIOWrite(1, 0xe0040008, 0x00001001);  // XFI, quad 0 fast2
      testPIOWrite(1, 0xe004010c, 0x00000000);  // XFI, quad 0 fast3, init pointers
      testPIOWrite(1, 0xe004000c, 0x00001801);  // XFI, quad 0 fast3
      testPIOWrite(1, 0xe0040300, 0x00000000);  // XFI, quad 0 inlv0, init pointers
      testPIOWrite(1, 0xe0040200, 0x00000401);  // XFI, quad 0 inlv0
      testPIOWrite(1, 0xe0040304, 0x00000000);  // XFI, quad 0 inlv1, init pointers
      testPIOWrite(1, 0xe0040204, 0x00000c01);  // XFI, quad 0 inlv1
      testPIOWrite(1, 0xe0040308, 0x00000000);  // XFI, quad 0 inlv0, init pointers
      testPIOWrite(1, 0xe0040208, 0x00001401);  // XFI, quad 0 inlv2
      testPIOWrite(1, 0xe004030c, 0x00000000);  // XFI, quad 0 inlv0, init pointers
      testPIOWrite(1, 0xe004020c, 0x00001c01);  // XFI, quad 0 inlv3
      
      testPIOWrite(1, 0xf0040800, 0x80000000);  // XFI, quad 1 ptm mode

      testPIOWrite(1, 0xf0040100, 0x00000000);  // XFI, quad 1 fast0, init pointers
      testPIOWrite(1, 0xf0040000, 0x00000001);  // XFI, quad 1 fast0
      testPIOWrite(1, 0xf0040104, 0x00000000);  // XFI, quad 1 fast0, init pointers
      testPIOWrite(1, 0xf0040004, 0x00000801);  // XFI, quad 1 fast1
      testPIOWrite(1, 0xf0040108, 0x00000000);  // XFI, quad 1 fast0, init pointers
      testPIOWrite(1, 0xf0040008, 0x00001001);  // XFI, quad 1 fast2
      testPIOWrite(1, 0xf004010c, 0x00000000);  // XFI, quad 1 fast0, init pointers
      testPIOWrite(1, 0xf004000c, 0x00001801);  // XFI, quad 1 fast3
      testPIOWrite(1, 0xf0040300, 0x00000000);  // XFI, quad 1 inlv0, init pointers
      testPIOWrite(1, 0xf0040200, 0x00000401);  // XFI, quad 1 inlv0
      testPIOWrite(1, 0xf0040304, 0x00000000);  // XFI, quad 1 inlv1, init pointers
      testPIOWrite(1, 0xf0040204, 0x00000c01);  // XFI, quad 1 inlv1
      testPIOWrite(1, 0xf0040308, 0x00000000);  // XFI, quad 1 inlv1, init pointers
      testPIOWrite(1, 0xf0040208, 0x00001401);  // XFI, quad 1 inlv2
      testPIOWrite(1, 0xf004030c, 0x00000000);  // XFI, quad 1 inlv1, init pointers
      testPIOWrite(1, 0xf004020c, 0x00001c01);  // XFI, quad 1 inlv3
      
      testPIOWrite(1, 0xe0000120, 0x80000000);  // UTX, quad 0 fast0
      testPIOWrite(1, 0xe0000124, 0x80000002);  // UTX, quad 0 fast1
      testPIOWrite(1, 0xe0000128, 0x80000004);  // UTX, quad 0 fast2
      testPIOWrite(1, 0xe000012c, 0x80000006);  // UTX, quad 0 fast3
      testPIOWrite(1, 0xe0000100, 0x80000001);  // UTX, quad 0 inlv0
      testPIOWrite(1, 0xe0000104, 0x80000003);  // UTX, quad 0 inlv1
      testPIOWrite(1, 0xe0000108, 0x80000005);  // UTX, quad 0 inlv2
      testPIOWrite(1, 0xe000010c, 0x80000007);  // UTX, quad 0 inlv3
      
      testPIOWrite(1, 0xe0000130, 0x80000008);  // UTX, quad 1 fast0
      testPIOWrite(1, 0xe0000134, 0x8000000a);  // UTX, quad 1 fast1
      testPIOWrite(1, 0xe0000138, 0x8000000c);  // UTX, quad 1 fast2
      testPIOWrite(1, 0xe000013c, 0x8000000e);  // UTX, quad 1 fast3
      testPIOWrite(1, 0xe0000110, 0x80000009);  // UTX, quad 1 inlv0
      testPIOWrite(1, 0xe0000114, 0x8000000b);  // UTX, quad 1 inlv1
      testPIOWrite(1, 0xe0000118, 0x8000000d);  // UTX, quad 1 inlv2
      testPIOWrite(1, 0xe000011c, 0x8000000f);  // UTX, quad 1 inlv3 
      
      testPIOWrite(1, 0xe0000200, 0x80000000);  // URX, quad 0 chan0
      testPIOWrite(1, 0xe0000204, 0x80000001);  // URX, quad 0 chan1
      testPIOWrite(1, 0xe0000208, 0x80000002);  // URX, quad 0 chan2
      testPIOWrite(1, 0xe000020c, 0x80000003);  // URX, quad 0 chan3
      testPIOWrite(1, 0xe0000210, 0x80000004);  // URX, quad 0 chan4
      testPIOWrite(1, 0xe0000214, 0x80000005);  // URX, quad 0 chan5
      testPIOWrite(1, 0xe0000218, 0x80000006);  // URX, quad 0 chan6
      testPIOWrite(1, 0xe000021c, 0x80000007);  // URX, quad 0 chan7
      testPIOWrite(1, 0xe0000220, 0x80000008);  // URX, quad 1 chan0
      testPIOWrite(1, 0xe0000224, 0x80000009);  // URX, quad 1 chan1
      testPIOWrite(1, 0xe0000228, 0x8000000a);  // URX, quad 1 chan2
      testPIOWrite(1, 0xe000022c, 0x8000000b);  // URX, quad 1 chan3
      testPIOWrite(1, 0xe0000230, 0x8000000c);  // URX, quad 1 chan4
      testPIOWrite(1, 0xe0000234, 0x8000000d);  // URX, quad 1 chan5
      testPIOWrite(1, 0xe0000238, 0x8000000e);  // URX, quad 1 chan6
      testPIOWrite(1, 0xe000023c, 0x8000000f);  // URX, quad 1 chan7

   
      testPIOWrite(1, 0xe000000c, 0x000040030); // HDE Soft Reset, chan 0

      testPIOWrite(1, 0xe0000504, 0x00000000); // HDE Soft Reset, chan 0
      testPIOWrite(1, 0xe0000508, 0x00007D7E); // HDLC AddrCntl, chan 0
      testPIOWrite(1, 0xe000050C, 0x00000020); // HDE Tx HWM, chan 0
      testPIOWrite(1, 0xe0000510, 0x05EE0030); // HDE Frame Size, chan 0
      testPIOWrite(1, 0xe0000500, 0x00210001); // HDE CNTL, chan 0
      
      testPIOWrite(1, 0xe0000604, 0x00000000); // HDE Soft Reset, chan 1
      testPIOWrite(1, 0xe0000608, 0x00000301); // HDLC AddrCntl, chan 1
      testPIOWrite(1, 0xe000060C, 0x00000020); // HDE Tx HWM, chan 1
      testPIOWrite(1, 0xe0000610, 0x05EE0030); // HDE Frame Size, chan 1
      testPIOWrite(1, 0xe0000600, 0x00210001); // HDE CNTL, chan 1
      
      testPIOWrite(1, 0xe0000704, 0x00000000); // HDE Soft Reset, chan 2
      testPIOWrite(1, 0xe0000708, 0x00000302); // HDLC AddrCntl, chan 2
      testPIOWrite(1, 0xe000070C, 0x00000020); // HDE Tx HWM, chan 2
      testPIOWrite(1, 0xe0000710, 0x05EE0030); // HDE Frame Size, chan 2
      testPIOWrite(1, 0xe0000700, 0x00210001); // HDE CNTL, chan 2
      
      testPIOWrite(1, 0xe0000804, 0x00000000); // HDE Soft Reset, chan 3
      testPIOWrite(1, 0xe0000808, 0x00000303); // HDLC AddrCntl, chan 3
      testPIOWrite(1, 0xe000080C, 0x00000020); // HDE Tx HWM, chan 3
      testPIOWrite(1, 0xe0000810, 0x05EE0030); // HDE Frame Size, chan 3
      testPIOWrite(1, 0xe0000800, 0x00210001); // HDE CNTL, chan 3
      
      testPIOWrite(1, 0xe0000904, 0x00000000); // HDE Soft Reset, chan 4
      testPIOWrite(1, 0xe0000908, 0x00000304); // HDLC AddrCntl, chan 4
      testPIOWrite(1, 0xe000090C, 0x00000020); // HDE Tx HWM, chan 4
      testPIOWrite(1, 0xe0000910, 0x05EE0030); // HDE Frame Size, chan 4
      testPIOWrite(1, 0xe0000900, 0x00210001); // HDE CNTL, chan 4
       
      testPIOWrite(1, 0xe0000a04, 0x00000000); // HDE Soft Reset, chan 5
      testPIOWrite(1, 0xe0000a08, 0x00000305); // HDLC AddrCntl, chan 5
      testPIOWrite(1, 0xe0000a0C, 0x00000020); // HDE Tx HWM, chan 5
      testPIOWrite(1, 0xe0000a10, 0x05EE0030); // HDE Frame Size, chan 5
      testPIOWrite(1, 0xe0000a00, 0x00210001); // HDE CNTL, chan 5
      
      testPIOWrite(1, 0xe0000b04, 0x00000000); // HDE Soft Reset, chan 6
      testPIOWrite(1, 0xe0000b08, 0x00000306); // HDLC AddrCntl, chan 6
      testPIOWrite(1, 0xe0000b0C, 0x00000020); // HDE Tx HWM, chan 6
      testPIOWrite(1, 0xe0000b10, 0x05EE0030); // HDE Frame Size, chan 6
      testPIOWrite(1, 0xe0000b00, 0x00210001); // HDE CNTL, chan 6

      testPIOWrite(1, 0xe0000c04, 0x00000000); // HDE Soft Reset, chan 7
      testPIOWrite(1, 0xe0000c08, 0x00000307); // HDLC AddrCntl, chan 7
      testPIOWrite(1, 0xe0000c0C, 0x00000020); // HDE Tx HWM, chan 7
      testPIOWrite(1, 0xe0000c10, 0x05EE0030); // HDE Frame Size, chan 7
      testPIOWrite(1, 0xe0000c00, 0x00210001); // HDE CNTL, chan 7

      testPIOWrite(1, 0xe0000d04, 0x00000000); // HDE Soft Reset, chan 8
      testPIOWrite(1, 0xe0000d08, 0x00000308); // HDLC AddrCntl, chan 8
      testPIOWrite(1, 0xe0000d0C, 0x00000020); // HDE Tx HWM, chan 8
      testPIOWrite(1, 0xe0000d10, 0x05EE0030); // HDE Frame Size, chan 8
      testPIOWrite(1, 0xe0000d00, 0x00210001); // HDE CNTL, chan 8

      testPIOWrite(1, 0xe0000e04, 0x00000000); // HDE Soft Reset, chan 9
      testPIOWrite(1, 0xe0000e08, 0x00000309); // HDLC AddrCntl, chan 9
      testPIOWrite(1, 0xe0000e0C, 0x00000020); // HDE Tx HWM, chan 9
      testPIOWrite(1, 0xe0000e10, 0x05EE0030); // HDE Frame Size, chan 9
      testPIOWrite(1, 0xe0000e00, 0x00210001); // HDE CNTL, chan 9

      testPIOWrite(1, 0xe0000f04, 0x00000000); // HDE Soft Reset, chan 10
      testPIOWrite(1, 0xe0000f08, 0x0000030a); // HDLC AddrCntl, chan 10
      testPIOWrite(1, 0xe0000f0C, 0x00000020); // HDE Tx HWM, chan 10
      testPIOWrite(1, 0xe0000f10, 0x05EE0030); // HDE Frame Size, chan 10
      testPIOWrite(1, 0xe0000f00, 0x00210001); // HDE CNTL, chan 10

      testPIOWrite(1, 0xe0001004, 0x00000000); // HDE Soft Reset, chan 11
      testPIOWrite(1, 0xe0001008, 0x0000030b); // HDLC AddrCntl, chan 11
      testPIOWrite(1, 0xe000100C, 0x00000020); // HDE Tx HWM, chan 11
      testPIOWrite(1, 0xe0001010, 0x05EE0030); // HDE Frame Size, chan 11
      testPIOWrite(1, 0xe0001000, 0x00210001); // HDE CNTL, chan 11

      testPIOWrite(1, 0xe0001104, 0x00000000); // HDE Soft Reset, chan 12
      testPIOWrite(1, 0xe0001108, 0x0000030c); // HDLC AddrCntl, chan 12
      testPIOWrite(1, 0xe000110C, 0x00000020); // HDE Tx HWM, chan 12
      testPIOWrite(1, 0xe0001110, 0x05EE0030); // HDE Frame Size, chan 12
      testPIOWrite(1, 0xe0001100, 0x00210001); // HDE CNTL, chan 12

      testPIOWrite(1, 0xe0001204, 0x00000000); // HDE Soft Reset, chan 13
      testPIOWrite(1, 0xe0001208, 0x0000030d); // HDLC AddrCntl, chan 13
      testPIOWrite(1, 0xe000120C, 0x00000020); // HDE Tx HWM, chan 13
      testPIOWrite(1, 0xe0001210, 0x05EE0030); // HDE Frame Size, chan 13
      testPIOWrite(1, 0xe0001200, 0x00210001); // HDE CNTL, chan 13

      testPIOWrite(1, 0xe0001304, 0x00000000); // HDE Soft Reset, chan 14
      testPIOWrite(1, 0xe0001308, 0x0000030e); // HDLC AddrCntl, chan 14
      testPIOWrite(1, 0xe000130C, 0x00000020); // HDE Tx HWM, chan 14
      testPIOWrite(1, 0xe0001310, 0x05EE0030); // HDE Frame Size, chan 14
      testPIOWrite(1, 0xe0001300, 0x00210001); // HDE CNTL, chan 14

      testPIOWrite(1, 0xe0001404, 0x00000000); // HDE Soft Reset, chan 15
      testPIOWrite(1, 0xe0001408, 0x0000030f); // HDLC AddrCntl, chan 15
      testPIOWrite(1, 0xe000140C, 0x00000020); // HDE Tx HWM, chan 15
      testPIOWrite(1, 0xe0001410, 0x05EE0030); // HDE Frame Size, chan 15
      testPIOWrite(1, 0xe0001400, 0x00210001); // HDE CNTL, chan 15
}
#endif

int bup_all_loopback()
{
  static U8 buf[32];
  U8 *pCmd;
  int uiCmd;

  printf("\nEnter the Port Number : ");
  gets(buf);
  pCmd = buf; 

  getInputValue (&pCmd, &uiCmd); 

  switch (uiCmd)
  { 
    case 1:
           testPIOWrite(1, 0xe0000120, 0x80001000);  // UTX, quad 0 fast0
           testPIOWrite(1, 0xe0000100, 0x80001001);  // UTX, quad 0 inlv0
           break;
    case 2:
           testPIOWrite(1, 0xe0000124, 0x80001002);  // UTX, quad 0 fast1
           testPIOWrite(1, 0xe0000104, 0x80001003);  // UTX, quad 0 inlv1
           break;
    case 3:
           testPIOWrite(1, 0xe0000128, 0x80001004);  // UTX, quad 0 fast2
           testPIOWrite(1, 0xe0000108, 0x80001005);  // UTX, quad 0 inlv2
           break;
    case 4:
           testPIOWrite(1, 0xe000012c, 0x80001006);  // UTX, quad 0 fast3
           testPIOWrite(1, 0xe000010c, 0x80001007);  // UTX, quad 0 inlv3
           break;
    case 5:
           testPIOWrite(1, 0xe0000130, 0x80001008);  // UTX, quad 1 fast0
           testPIOWrite(1, 0xe0000110, 0x80001009);  // UTX, quad 1 inlv0
           break;
    case 6:
           testPIOWrite(1, 0xe0000134, 0x8000100a);  // UTX, quad 1 fast1
           testPIOWrite(1, 0xe0000114, 0x8000100b);  // UTX, quad 1 inlv1
           break;
    case 7:
           testPIOWrite(1, 0xe0000138, 0x8000100c);  // UTX, quad 1 fast2
           testPIOWrite(1, 0xe0000118, 0x8000100d);  // UTX, quad 1 inlv2
           break;
    case 8:
           testPIOWrite(1, 0xe000013c, 0x8000100e);  // UTX, quad 1 fast3
           testPIOWrite(1, 0xe000011c, 0x8000100f);  // UTX, quad 1 inlv3 
           break;
  }

  return (0);
      
}
void bup_stats_phe (unsigned int chan)
{

unsigned int chanBase, i; 
unsigned int stat[15];

	switch(chan) {
		case 0 : chanBase = 0xe0000500; break;
		case 1 : chanBase = 0xe0000600; break;
		case 2 : chanBase = 0xe0000700; break;
		case 3 : chanBase = 0xe0000800; break;
		case 4 : chanBase = 0xe0000900; break;
		case 5 : chanBase = 0xe0000a00; break;
		case 6 : chanBase = 0xe0000b00; break;
		case 7 : chanBase = 0xe0000c00; break;
		case 8 : chanBase = 0xe0000d00; break;
		case 9 : chanBase = 0xe0000e00; break;
		case 10 : chanBase = 0xe0000f00; break;
		case 11 : chanBase = 0xe0001000; break;
		case 12 : chanBase = 0xe0001100; break;
		case 13 : chanBase = 0xe0001200; break;
		case 14 : chanBase = 0xe0001300; break;
		case 15 : chanBase = 0xe0001400; break;	
		default : chanBase = 0xe0000500; break;
		}
	
	for(i=0;i<=14; i++) 
		//stat[i] = tprr(1, chanBase + 0x14 + (i*4));
		stat[i] = testPIORead1(1, chanBase + 0x14 + (i*4));
	printf("------------------------------------\n");
	printf("TxFrameCnt      = %u\n", stat[0]);
	printf("TxByteCnt       = %u\n", stat[1]);
	printf("TxTERRCnt       = %u\n", stat[2]);
	printf("TxShortFrameCnt = %u\n", stat[3]);
	printf("TxLongFrameCnt  = %u\n", stat[4]);
	printf("TxIFErrCnt      = %u\n", stat[5]);
	printf("TxDropFrameCnt  = %u\n", stat[6]);
	printf("\n");
	printf("RxFrameCnt      = %u\n", stat[7]);
	printf("RxByteCnt       = %u\n", stat[8]);
	printf("RxCrcErrCnt     = %u\n", stat[9]);
	printf("RxShortFrameCnt = %u\n", stat[10]);
	printf("RxLongFrameCnt  = %u\n", stat[11]);
	printf("RxDropFrameCnt  = %u\n", stat[12]);
	printf("\n");
	printf("TxMemWrWrap = %u, TxMemWrPtr = %u\n", (stat[13]&0x3ff)>>9,stat[13]&0x1ff);
	printf("TxMemRdWrap = %u, TxMemRdPtr = %u\n", (stat[13]&0x03ffffff)>>25, (stat[13]&0x01ffffff)>>16);
	printf("\n");
	printf("RxMemWrWrap = %u, RxMemWrPtr = %u\n", (stat[14]&0x3ff)>>9,stat[14]&0x1ff);
	printf("RxMemRdWrap = %u, RxMemRdPtr = %u\n", (stat[14]&0x03ffffff)>>25,(stat[14]&0x01ffffff)>>16);
	printf("------------------------------------\n");

}
static int bup_PL2CntList()
{
   static U8 buf[32];
   U8 *pCmd;
   int uiCmd;

    printf("\nEnter the Channel Number : ");
    gets(buf);
    pCmd = buf; 

    getInputValue (&pCmd, &uiCmd); 
    bup_stats_phe(uiCmd); 

    return 0;
}

void bup_all_stats_phe ()
{

unsigned int chanBase, i, chan = 0; 
unsigned int stat[15][8]; // 15 counters, 8 channels

#ifndef CPE_50
for(chan=0;chan<=7;chan++)
#endif
{
	switch(chan) {
		case 0 : chanBase = 0xe0000500; break;
		case 1 : chanBase = 0xe0000600; break;
		case 2 : chanBase = 0xe0000700; break;
		case 3 : chanBase = 0xe0000800; break;
		case 4 : chanBase = 0xe0000900; break;
		case 5 : chanBase = 0xe0000a00; break;
		case 6 : chanBase = 0xe0000b00; break;
		case 7 : chanBase = 0xe0000c00; break;
		case 8 : chanBase = 0xe0000d00; break;
		case 9 : chanBase = 0xe0000e00; break;
		case 10 : chanBase = 0xe0000f00; break;
		case 11 : chanBase = 0xe0001000; break;
		case 12 : chanBase = 0xe0001100; break;
		case 13 : chanBase = 0xe0001200; break;
		case 14 : chanBase = 0xe0001300; break;
		case 15 : chanBase = 0xe0001400; break;	
		default : chanBase = 0xe0000500; break;
		}
	
	for(i=0;i<=14; i++) 
		//stat[i][chan] = tprr(1, chanBase + 0x14 + (i*4));
		stat[i][chan] = testPIORead1 (1, chanBase + 0x14 + (i*4));
}

	printf("---------------------------------------------------------------------------------\n");
	printf("Cnt           ch0     ch1      ch2      ch3      ch4      ch5      ch6      ch7\n");  
	printf("TxFrameCnt  = %d      %d       %d       %d       %d       %d       %d       %d \n", 
	stat[0][0], stat[0][1], stat[0][2], stat[0][3], stat[0][4], stat[0][5], stat[0][6], stat[0][7]);

	printf("---------------------------------------------------------------------------------\n");

}

#endif // #ifdef CO_30_DIAGS
