/**************************************************************
***************************************************************
**
** Host Application, Copyright (C) 2000-2002
** Ikanos Communication, Fremont, CA 
** All rights reserved.
**
** The information and contents of this file are the
** proprietary information of Ikanos Communication and may not
** be disclosed or used without the formal written approval of 
** Ikanos Communication
**
***************************************************************

$Revision: 1.1 $
$Date: 2006/10/16 04:34:50 $
**************************************************************/

#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "dtypes.h"
#include "pio_defines.h"
#include "membase_defines.h"
#include "verilog_test.h"

#include "piotst.h" 
#include "scale.h" 
#include "mem.h"
#include "diag.h"
#include "bitmask.h" 
                            
#define _DEBUG

extern void doDmaWrite(UINT32 destAddr, BYTE *dataPtr, UINT32 dataLen, int destFifoFlag); 

extern void read_bytes_to_buffer(
			int srcAddr, 
			int size, /*size in bytes*/
			int fifo_transaction, /*set to 1 if source is a fifo*/
			int channel_num /*set only if fifo_transaction bit is set to 1*/
			);
extern void tc_loopback1_stm_x2c_ilv();
extern char DmaReadBuffer[];

extern int fnum;

char DmaWriteBuffer[64];
int  failFlag = OK;

UINT32 testVbusIFEReg();
UINT32 rd0Reg(UINT32 adr);
UINT32 readVbus0Reg();
UINT32 wt0Reg(UINT32 adr, UINT32 dt);
void configVbus0();

void init_buff(void)
{
int n;

    /******************************/
    /* Host to Ext Mem DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    for (n=0; n<0x20; n++) {
        DmaWriteBuffer[n] = n;
    }
}


int xfifo_fast_mem_test(void)
{
    init_buff();

    /******************************/
    /* Host to XFIFO Fast memory ..... */
    /******************************/
    /* Setting Up XFIFO ..... */
    pio_write( XFIFOF_CXFT_B, 0x00000000);

    pio_write( XFIFOF_CXFT_A, 0x0000002f);

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(DMA_MEM_ADR, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from XFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(DMA_MEM_ADR, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nXFIFO FAST MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
        printf("\n\nXFIFO FAST MEM TEST FAILED. \n");
        return ERROR;
    }
}

int xfifo_inter_test(void)
{
    init_buff();

    /******************************/
    /* Host to XFIFO Interleaver DMA ..... */
    /******************************/
    /* Setting Up XFIFO ..... */
    pio_write( XFIFOI_CXFT_B, 0x00000000);

    pio_write( XFIFOI_CXFT_A, 0x0000002f);

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_XFIFO_INTERLEAVE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from XFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(ADDRESS_XFIFO_INTERLEAVE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nXFIFO ILV MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nXFIFO ILV MEM TEST FAILED. \n");
        return ERROR;
    }
}                  

int ext_test(void)
{
    init_buff();

    /******************************/
    /* Host to Ext Mem DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(CODE_MEMORY_ADR, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from XFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(CODE_MEMORY_ADR, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nEXTERNAL MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nEXTERNAL MEM TEST FAILED. \n");
        return ERROR;
    }
}

int fmc_i_test(void)
{
    init_buff();

    /******************************/
    /* Host to FMC I$ DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_FRAMER_ICACHE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from XFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(ADDRESS_FRAMER_ICACHE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nFMC ICACHE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nFMC ICACHE MEM TEST FAILED. \n");
        return ERROR;
    }
}

int fmc_d_test(void)
{
    init_buff();

    /******************************/
    /* Host to FMC D$ DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_FRAMER_DCACHE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from XFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(ADDRESS_FRAMER_DCACHE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nFMC DCACHE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nFMC DCACHE MEM TEST FAILED. \n");
        return ERROR;
    }
}

int Yfifo_fast_mem_test(void)
{
    init_buff();

    /******************************/
    /* Host to YFIFO Fast memory ..... */
    /******************************/
    /* Setting Up YFIFO ..... */
    pio_write( YFIFO_TOFT, 0x00000007);

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_YFIFO_TONEORDER*/
    doDmaWrite(ADDRESS_YFIFO_TONEORDER, & DmaWriteBuffer[0], 0x20, 1);

    /******************************/
    /* Transferring data from YFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_YFIFO_TONEORDER*/
    read_bytes_to_buffer(ADDRESS_YFIFO_TONEORDER, 0x20, 1, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nYFIFO FAST MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nYFIFO FAST MEM TEST FAILED. \n");
        return ERROR;
    }
}

int yfifo_inter_test(void)
{
    init_buff();

    /******************************/
    /* Host to YFIFO Interleaver DMA ..... */
    /******************************/
    /* Setting Up YFIFO ..... */
    pio_write( YFIFO_CYFT_A, 0x0000004f);

    pio_write( YFIFO_CYFT_B, 0x00000000);

    pio_write( YFIFO_CYFT_C, 0x077d0000);

    pio_write( YFIFO_CYFT_D, 0x00000000);

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_YFIFO_INTERLEAVE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(ADDRESS_YFIFO_INTERLEAVE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nYFIFO ILV MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nYFIFO ILV MEM TEST FAILED. \n");
        return ERROR;
    }
}

int tone_table_test(void)
{
    init_buff();

    /******************************/
    /* Host to Mapper Tone Order Table DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_MAPPERTONEORDER, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(ADDRESS_MAPPERTONEORDER, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nMAPPER TONE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nMAPPER TONE MEM TEST FAILED. \n");
        return ERROR;
    }
}


int mapper_gain_test(void)
{
    init_buff();

    /******************************/
    /* Host to Mapper Gain Scale Table DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_GAINTABLE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(ADDRESS_GAINTABLE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nMAPPER GAIN MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nMAPPER GAIN MEM TEST FAILED. \n");
        return ERROR;
    }
}

int zfifo_mem_test(void)
{
    init_buff();

    /******************************/
    /* Host to ZFIFO Interleaver DMA ..... */
    /******************************/
    /* Setting Up ZFIFO ..... */
    pio_write( ZFIFO_CZFT_A, 0x0000003f);

    pio_write( ZFIFO_CZFT_C, 0x00000000);

    pio_write( ZFIFO_CZFT_D, 0x00000000);

    /*DMA data from DmaWriteBuffer to Addr = 0xc3000000*/
    doDmaWrite(ADDRESS_ZFIFO, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = 0xc3000000*/
    read_bytes_to_buffer(ADDRESS_ZFIFO, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nZFIFO MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nZFIFO MEM TEST FAILED. \n");
        return ERROR;
    }
}

int cfifo_mem_test(void)
{
    init_buff();

    /******************************/
    /* Host to CFIFO mem DMA ..... */
    /******************************/
    /* Setting Up CFIFO ..... */
    pio_write( CCFT0_B, 0x00000000);

    pio_write( CCFT0_A, 0x0000002f);

    /*DMA data from DmaWriteBuffer to Addr = 0xc6000000*/
    doDmaWrite(ADDRESS_CFIFOBANKA, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from zFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = 0xc6000000*/
    read_bytes_to_buffer(ADDRESS_CFIFOBANKA, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nCFIFO MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nCFIFO MEM TEST FAILED. \n");
        return ERROR;
    }
}

int dmc_i_test(void)
{
    init_buff();

    /******************************/
    /* Host to DMC I$ DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_DEMAPPERCPU_ICACHE*/
    doDmaWrite(ADDRESS_DEMAPPERCPU_ICACHE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_DEMAPPERCPU_ICACHE*/
    read_bytes_to_buffer(ADDRESS_DEMAPPERCPU_ICACHE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nDMC ICACHE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nDMC ICACHE MEM TEST FAILED. \n");
        return ERROR;
    }
}

int dmc_d_test(void)
{
    init_buff();

    /******************************/
    /* Host to DMC D$ DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_DEMAPPERCPU_DCACHE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from XFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = DMA_MEM_ADR*/
    read_bytes_to_buffer(ADDRESS_DEMAPPERCPU_DCACHE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nDMC DCACHE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nDMC DCACHE MEM TEST FAILED. \n");
        return ERROR;
    }
}

int smc_snr_test(void)
{
    
    init_buff();

    /******************************/
    /* Host to SMC SNR Memory DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = DMA_MEM_ADR*/
    doDmaWrite(ADDRESS_SMCONTROLSNRMEMORY, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_SMCONTROLSNRMEMORY*/
    read_bytes_to_buffer(ADDRESS_SMCONTROLSNRMEMORY, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nSMC SNR MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nSMC SNR MEM TEST FAILED. \n");
        return ERROR;
    }
}

int smc_tone_test(void)
{
    
    init_buff();
#ifdef BME_CPE_20

    /******************************/
    /* Host to SMC Tone Memory DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_SMCONTROLTONEMEMORY*/
    doDmaWrite(ADDRESS_SMCONTROLTONEMEMORY, & DmaWriteBuffer[0], 12, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_SMCONTROLTONEMEMORY*/
    read_bytes_to_buffer(ADDRESS_SMCONTROLTONEMEMORY, 12, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 12)) {
	    printf("\n\nSMC TONE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nSMC TONE MEM TEST FAILED. \n");
        return ERROR;
    }
#else

    /******************************/
    /* Host to SMC Tone Memory DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_SMCONTROLTONEMEMORY*/
    doDmaWrite(ADDRESS_SMCONTROLTONEMEMORY, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_SMCONTROLTONEMEMORY*/
    read_bytes_to_buffer(ADDRESS_SMCONTROLTONEMEMORY, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nSMC TONE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nSMC TONE MEM TEST FAILED. \n");
        return ERROR;
    }
#endif
}

int smc_thres_test(void)
{
    
    init_buff();

#ifdef BME_CPE_20
    /******************************/
    /* Host to SMC Threshold Memory DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = 0xd2002180*/
    doDmaWrite(ADDRESS_SMCONTROLTHRESMEMORY, & DmaWriteBuffer[0], 12, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_SMCONTROLTHRESMEMORY*/
    read_bytes_to_buffer(ADDRESS_SMCONTROLTHRESMEMORY, 12, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 12)) {
	    printf("\n\nSMC Threshold MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nSMC Threshold MEM TEST FAILED. \n");
        return ERROR;
    }
#else
    /******************************/
    /* Host to SMC Threshold Memory DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_SMCONTROLTHRESMEMORY*/
    doDmaWrite(ADDRESS_SMCONTROLTHRESMEMORY, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_SMCONTROLTHRESMEMORY*/
    read_bytes_to_buffer(ADDRESS_SMCONTROLTHRESMEMORY, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nSMC Threshold MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nSMC Threshold MEM TEST FAILED. \n");
        return ERROR;
    }
#endif
}

int bfifo_fast_mem_test(void)
{
    init_buff();

    /******************************/
    /* Host to BFIFO Fast memory ..... */
    /******************************/
    /* Setting Up bFIFO ..... */
    pio_write( CBFT_B, 0x00000000);

    pio_write( CBFT_A, 0x00000027);

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_BFIFOFAST*/
    doDmaWrite(ADDRESS_BFIFOFAST, & DmaWriteBuffer[0], 0x20, 1);

    /******************************/
    /* Transferring data from BFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_BFIFOFAST*/
    read_bytes_to_buffer(ADDRESS_BFIFOFAST, 0x20, 1, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nBFIFO FAST MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nBFIFO FAST MEM TEST FAILED. \n");
        return ERROR;
    }
}

int bfifo_inter_test(void)
{
    init_buff();

    /******************************/
    /* Host to BFIFO Interleaver DMA ..... */
    /******************************/
    /* Setting Up BFIFO ..... */
    pio_write( CBIT_B, 0x00000000);

    pio_write( CBIT_C, 0x01800000);

    pio_write( CBIT_D, 0x00000000);

    pio_write( CBIT_A, 0x00000047);

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_BFIFOINTERLEAVE*/
    doDmaWrite(ADDRESS_BFIFOINTERLEAVE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_BFIFOINTERLEAVE*/
    read_bytes_to_buffer(ADDRESS_BFIFOINTERLEAVE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nBFIFO ILV MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nBFIFO ILV MEM TEST FAILED. \n");
        return ERROR;
    }
}

int bfifo_demapper_test(void)
{
    init_buff();

    /******************************/
    /* Host to BFIFO Demapper Memory DMA ..... */
    /******************************/
    /* Setting Up BFIFO ..... */
    pio_write( CDMT, 0x00000007);

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_BFIFODEMAPPER*/
    doDmaWrite(ADDRESS_BFIFODEMAPPER, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_BFIFODEMAPPER*/
    read_bytes_to_buffer(ADDRESS_BFIFODEMAPPER, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nBFIFO DEMAPPER MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nBFIFO DEMAPPER MEM TEST FAILED. \n");
        return ERROR;
    }
}

int demapper_test(void)
{
    init_buff();

    /******************************/
    /* Host to Demapper (ROT) Memory DMA ..... */
    /******************************/

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_DEMAPPERTONEORDER*/
    doDmaWrite(ADDRESS_DEMAPPERTONEORDER, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_DEMAPPERTONEORDER*/
    read_bytes_to_buffer(ADDRESS_DEMAPPERTONEORDER, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nDEMAPPER ROT MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nDEMAPPER ROT MEM TEST FAILED. \n");
        return ERROR;
    }
}

int feq_test(void)
{
    init_buff();
#ifndef BME_CPE_20

    /******************************/
    /* Host to FEQ Table DMA ..... */
    /******************************/

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_FEQ_TABLE_FINE_S16*/
    doDmaWrite(ADDRESS_FEQ_TABLE_FINE_S16, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_FEQ_TABLE_FINE_S16*/
    read_bytes_to_buffer(ADDRESS_FEQ_TABLE_FINE_S16, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nFEQ MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nFEQ MEM TEST FAILED. \n");
        return ERROR;
    }
#else

    /******************************/
    /* Host to FEQ Table DMA ..... */
    /******************************/

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_FEQ_TABLE_FINE_S16*/
    doDmaWrite(ADDRESS_FEQ_TABLE_FINE_S16, & DmaWriteBuffer[0], 12, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_FEQ_TABLE_FINE_S16*/
    read_bytes_to_buffer(ADDRESS_FEQ_TABLE_FINE_S16, 12, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 12)) {
	    printf("\n\nFEQ MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nFEQ MEM TEST FAILED. \n");
        return ERROR;
    }
#endif    
}

int teq_test(void)
{
    init_buff();

    /******************************/
    /* Host to TEQ Coeff Table DMA ..... */
    /******************************/

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_TEQ_TABLE*/
    doDmaWrite(ADDRESS_TEQ_TABLE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_TEQ_TABLE*/
    read_bytes_to_buffer(ADDRESS_TEQ_TABLE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nTEQ MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nTEQ MEM TEST FAILED. \n");
        return ERROR;
    }
}

int rmc_i_test(void)
{
    init_buff();

    /******************************/
    /* Host to RMC I$ DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_RXCPU_ICACHE*/
    doDmaWrite(ADDRESS_RXCPU_ICACHE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_RXCPU_ICACHE*/
    read_bytes_to_buffer(ADDRESS_RXCPU_ICACHE, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nRMC ICACHE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nRMC ICACHE MEM TEST FAILED. \n");
        return ERROR;
    }
}

int rmc_d_test(void)
{
    init_buff();

    /******************************/
    /* Host to RMC D$ DMA ..... */

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_RXCPU_DCACHE*/
    doDmaWrite(ADDRESS_RXCPU_DCACHE, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from XFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_RXCPU_DCACHE*/
    read_bytes_to_buffer(ADDRESS_RXCPU_DCACHE, 0x20, 0, 0);

   if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nRMC DCACHE MEM TEST PASSED. \n");
        return OK;
    }
    else {
        fnum++;
	    printf("\n\nRMC DCACHE MEM TEST FAILED. \n");
        return ERROR;
    }
}

int afifo_mem_test(void)
{
    init_buff();

    /******************************/
    /* Host to AFIFO DMA ..... */
    /* Program AFIFO Registers AFIFO DMA ..... */
    pio_write( CAFT_A, 0x0000003f);

    pio_write( CAFT_B, 0x00000000);

    pio_write( CAFT_C, 0x00000000);

    pio_write( CAFT_D, 0x00000000);

    /*DMA data from DmaWriteBuffer to Addr = ADDRESS_AFIFO*/
    doDmaWrite(ADDRESS_AFIFO, & DmaWriteBuffer[0], 0x20, 0);

    /******************************/
    /* Transferring data from BFIFO to Host .... */
    /*Reading bytes to DmaReadBuffer from Addr = ADDRESS_AFIFO*/
    read_bytes_to_buffer(ADDRESS_AFIFO, 0x20, 0, 0);

    if (!memcmp(&DmaWriteBuffer[0], &DmaReadBuffer[0], 0x20)) {
	    printf("\n\nAFIFO FAST MEM TEST PASSED. \n");
         return OK;
     }
     else {
         fnum++;
         printf("\n\nAFIFO FAST MEM TEST FAILED. \n");
         return ERROR;
     }
}

void bme_dma_test(void)
{
    xfifo_fast_mem_test();
    xfifo_inter_test();
    ext_test();
    fmc_i_test();
    fmc_d_test();
    Yfifo_fast_mem_test();
    yfifo_inter_test();
    tone_table_test();
    mapper_gain_test();
    zfifo_mem_test();
    cfifo_mem_test();
    dmc_i_test();
    dmc_d_test();
    smc_snr_test();
    smc_tone_test();
    smc_thres_test();
    bfifo_fast_mem_test();
    bfifo_inter_test();
    bfifo_demapper_test();
    demapper_test();
    feq_test();
    teq_test();
    rmc_i_test();
    rmc_d_test();
    afifo_mem_test();
}
/************************************************************/

int ref_afe_vbus0_pio_rw (int afenum) {

    UINT32 ret=0;
    int status=0;

    configVbus0();
    ret = readVbus0Reg(afenum);
    if (ret) {
        printf("\nAFE register test passed!\n"); 
    }
    else {
        status = 1;
        printf("\nAFE register test failed!\n"); 
    }
    ret = testVbusIFEReg(afenum);
    if (ret) {
        printf("\nIFE register test passed!\n"); 
    }
    else {
        status = 1;
        printf("\nIFE register test failed!\n"); 
    }
    if (!status) {
        return OK;
    }
    else {
        fnum++;
        return ERROR;
    }
}


/************************************************************/
int vbus0_test(void)
{
    return(ref_afe_vbus0_pio_rw (0));
}

/************************************************************/
void configVbus0(){

/******************************/
/* Configuring BME to run at 96 MHz ..... */
pio_write (0xe0070008,0x0000012f);


/******************************/
/* Configuring VIF Registers ..... */
pio_write( VIF_ICCR, 0x00700070);

pio_write( VIF_SCCR, 0x1f1f0303);

pio_write( VIF_CST, 0x00000000);

pio_write( VIF_CST0H, 0x40404041);

pio_write( VIF_CST1L, 0x00000000);

pio_write( VIF_CST1H, 0x40404041);

pio_write( VIF_CST2L, 0x00000000);

pio_write( VIF_CST2H, 0x40404040);

pio_write( VIF_CST3L, 0x00000000);

pio_write( VIF_CST3H, 0x40404040);

pio_write( VIF_CST4L, 0x00000000);

pio_write( VIF_CST4H, 0x40404040);

pio_write( VIF_CST5L, 0x00000000);

pio_write( VIF_CST5H, 0x40404040);

pio_write( VIF_CST6L, 0x00000000);

pio_write( VIF_CST6H, 0x40404040);

pio_write( VIF_CST7L, 0x00000000);

pio_write( VIF_CST7H, 0x40404040);

pio_write( VIF_CST8L, 0x00000001);

pio_write( VIF_CST8H, 0x40404041);

pio_write( VIF_CST9L, 0x00000001);

pio_write( VIF_CST9H, 0x40404041);

pio_write( VIF_CST10L, 0x00000001);

pio_write( VIF_CST10H, 0x40404040);

pio_write( VIF_CST11L, 0x00000001);

pio_write( VIF_CST11H, 0x40404040);

pio_write( VIF_CST12L, 0x00000001);

pio_write( VIF_CST12H, 0x40404040);

pio_write( VIF_CST13L, 0x00000001);

pio_write( VIF_CST13H, 0x40404040);

pio_write( VIF_CST14L, 0x00000001);

pio_write( VIF_CST14H, 0x40404040);

pio_write( VIF_CST15L, 0x00000001);

pio_write( VIF_CST15H, 0x40404040);

pio_write( VIF_CST16L, 0x00000108);

pio_write( VIF_CST16H, 0x40404041);

pio_write( VIF_CST17L, 0x00000108);

pio_write( VIF_CST17H, 0x40404041);

pio_write( VIF_CST18L, 0x00000108);

pio_write( VIF_CST18H, 0x40404040);

pio_write( VIF_CST19L, 0x00000108);

pio_write( VIF_CST19H, 0x40404040);

pio_write( VIF_CST20L, 0x00000108);

pio_write( VIF_CST20H, 0x40404040);

pio_write( VIF_CST21L, 0x00000108);

pio_write( VIF_CST21H, 0x40404040);

pio_write( VIF_CST22L, 0x00000108);

pio_write( VIF_CST22H, 0x40404040);

pio_write( VIF_CST23L, 0x00000108);

pio_write( VIF_CST23H, 0x40404040);

pio_write( VIF_CST24L, 0x00000109);

pio_write( VIF_CST24H, 0x40404041);

pio_write( VIF_CST25L, 0x00000109);

pio_write( VIF_CST25H, 0x40404041);

pio_write( VIF_CST26L, 0x00000109);

pio_write( VIF_CST26H, 0x40404040);

pio_write( VIF_CST27L, 0x00000109);

pio_write( VIF_CST27H, 0x40404040);

pio_write( VIF_CST28L, 0x00000109);

pio_write( VIF_CST28H, 0x40404040);

pio_write( VIF_CST29L, 0x00000109);

pio_write( VIF_CST29H, 0x40404040);

pio_write( VIF_CST30L, 0x00000109);

pio_write( VIF_CST30H, 0x40404040);

pio_write( VIF_CST31L, 0x00000109);

pio_write( VIF_CST31H, 0x40404040);

/******************************/
/* Enabling V-bus0 ..... */
pio_write( 0xe0018000, 0x80000000);

}

UINT32 testVbusIFEReg(int afenum)
{
    UINT32 ret=0;

	printf ("\nChecking Channel 0 IFE gain control registers\n");
    wt0Reg(0x20 + afenum, 0xa5a5a5a5);
    rd0Reg(0x20 + afenum);
    ret |= pio_read_check(VIF_RRCR, 0xa5a5a5a5);

    wt0Reg(0x21 + afenum, 0x5a5a5a5a);
    rd0Reg(0x21 + afenum);
    ret |= pio_read_check(VIF_RRCR, 0x5a5a5a5a);

	printf ("\nChecking Channel 1 IFE transmit gain control register\n");
    wt0Reg(0x22 + afenum, 0xa5a5a5a5);
    rd0Reg(0x22 + afenum);
    ret |= pio_read_check(VIF_RRCR, 0xa5a5a5a5);

	printf ("\nChecking Channel 1 IFE receive gain control register\n");
    wt0Reg(0x23 + afenum, 0x5a5a5a5a);
    rd0Reg(0x23 + afenum);
    ret |= pio_read_check(VIF_RRCR, 0x5a5a5a5a);

	printf ("\nChecking IFE transfer status register\n");
    wt0Reg(0x24 + afenum, 0xa5a5a5a5);
    rd0Reg(0x24 + afenum);
    ret |= pio_read_check(VIF_RRCR, 0xa5a5a5a5);
    return ret;
}

/******************************/
/* Reading V-bus0 register  ..... */
/******************************/
UINT32 rd0Reg(UINT32 adr){

UINT32 reg, status;

    pio_write( VIF_RWCR, _bit31+adr);
    pio_read (VIF_RASR, (&status));

    while((status & _bit31) ==0 )
	    pio_read (VIF_RASR, (&status));

    pio_read(VIF_RRCR, &reg);
    return reg;

}

/******************************/
/* Writing V-bus0 register  ..... */
/******************************/

UINT32 wt0Reg(UINT32 adr, UINT32 dt){

UINT32 status;

pio_read (VIF_RASR, (&status));
while((status & _bit30) !=0 )
	pio_read (VIF_RASR, (&status));

pio_write( VIF_RWDR, dt);

pio_read (VIF_RASR, (&status));
while((status & _bit30) !=0 )
	pio_read (VIF_RASR, (&status));

pio_write( VIF_RWCR, _bit30+adr);

pio_read (VIF_RASR, (&status));
while((status & _bit30) !=0 )
	pio_read (VIF_RASR, (&status));

    return status;

}

UINT32 readVbus0Reg(int afenum){

UINT32 afe_vbus0_ccr_status, ret=0;

printf ("\nChecking PIO access of VBUS 0 AFE %x registers 0x80 to 0x89", afenum);

/******************************/
/* Writing V-bus0 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWDR, 0x00005a56);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWCR, 0x40000086 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

/******************************/
/* Reading V-bus0 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000086 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

ret = pio_read_check(VIF_RRCR, 0x00005a56);

/******************************/
/* Writing V-bus0 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWDR, 0x00005a57);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWCR, 0x40000087 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

/******************************/
/* Reading V-bus0 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000087 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

ret = pio_read_check(VIF_RRCR, 0x00005a57);

/******************************/
/* Writing V-bus0 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWDR, 0x00005a58);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWCR, 0x40000088 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

/******************************/
/* Reading V-bus0 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000088 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

ret = pio_read_check(VIF_RRCR, 0x00005a58);


/******************************/
/* Writing V-bus0 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWDR, 0x00005a59);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

pio_write( VIF_RWCR, 0x40000089 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

/******************************/
/* Reading V-bus0 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000089 + afenum);

pio_read (VIF_RASR, (&afe_vbus0_ccr_status));
while((afe_vbus0_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus0_ccr_status));

ret = pio_read_check(VIF_RRCR, 0x00005a59);
  
return ret;

}/*end of test*/


void configVbus1()
{
/******************************/
/* Configuring BME to run at 96 MHz ..... */
pio_write (CKM_PCR,0x0000012f);


/******************************/
/* Configuring VIF Registers ..... */
pio_write( VIF_ICCR, 0x00700070);

pio_write( VIF_SCCR, 0x1f1f0303);

pio_write( VIF_CST, 0x00000000);

pio_write( VIF_CST0H, 0x40404041);

pio_write( VIF_CST1L, 0x00000000);

pio_write( VIF_CST1H, 0x40404041);

pio_write( VIF_CST2L, 0x00000000);

pio_write( VIF_CST2H, 0x40404040);

pio_write( VIF_CST3L, 0x00000000);

pio_write( VIF_CST3H, 0x40404040);

pio_write( VIF_CST4L, 0x00000000);

pio_write( VIF_CST4H, 0x40404040);

pio_write( VIF_CST5L, 0x00000000);

pio_write( VIF_CST5H, 0x40404040);

pio_write( VIF_CST6L, 0x00000000);

pio_write( VIF_CST6H, 0x40404040);

pio_write( VIF_CST7L, 0x00000000);

pio_write( VIF_CST7H, 0x40404040);

pio_write( VIF_CST8L, 0x00000001);

pio_write( VIF_CST8H, 0x40404041);

pio_write( VIF_CST9L, 0x00000001);

pio_write( VIF_CST9H, 0x40404041);

pio_write( VIF_CST10L, 0x00000001);

pio_write( VIF_CST10H, 0x40404040);

pio_write( VIF_CST11L, 0x00000001);

pio_write( VIF_CST11H, 0x40404040);

pio_write( VIF_CST12L, 0x00000001);

pio_write( VIF_CST12H, 0x40404040);

pio_write( VIF_CST13L, 0x00000001);

pio_write( VIF_CST13H, 0x40404040);

pio_write( VIF_CST14L, 0x00000001);

pio_write( VIF_CST14H, 0x40404040);

pio_write( VIF_CST15L, 0x00000001);

pio_write( VIF_CST15H, 0x40404040);

pio_write( VIF_CST16L, 0x00000108);

pio_write( VIF_CST16H, 0x40404041);

pio_write( VIF_CST17L, 0x00000108);

pio_write( VIF_CST17H, 0x40404041);

pio_write( VIF_CST18L, 0x00000108);

pio_write( VIF_CST18H, 0x40404040);

pio_write( VIF_CST19L, 0x00000108);

pio_write( VIF_CST19H, 0x40404040);

pio_write( VIF_CST20L, 0x00000108);

pio_write( VIF_CST20H, 0x40404040);

pio_write( VIF_CST21L, 0x00000108);

pio_write( VIF_CST21H, 0x40404040);

pio_write( VIF_CST22L, 0x00000108);

pio_write( VIF_CST22H, 0x40404040);

pio_write( VIF_CST23L, 0x00000108);

pio_write( VIF_CST23H, 0x40404040);

pio_write( VIF_CST24L, 0x00000109);

pio_write( VIF_CST24H, 0x40404041);

pio_write( VIF_CST25L, 0x00000109);

pio_write( VIF_CST25H, 0x40404041);

pio_write( VIF_CST26L, 0x00000109);

pio_write( VIF_CST26H, 0x40404040);

pio_write( VIF_CST27L, 0x00000109);

pio_write( VIF_CST27H, 0x40404040);

pio_write( VIF_CST28L, 0x00000109);

pio_write( VIF_CST28H, 0x40404040);

pio_write( VIF_CST29L, 0x00000109);

pio_write( VIF_CST29H, 0x40404040);

pio_write( VIF_CST30L, 0x00000109);

pio_write( VIF_CST30H, 0x40404040);

pio_write( VIF_CST31L, 0x00000109);

pio_write( VIF_CST31H, 0x40404040);

/******************************/
/* Enabling V-bus1 ..... */
pio_write( 0xe0018000, _bit30);

}

int ref_afe_vbus1_pio_rw(int afenum) 
{ 
UINT32 afe_vbus1_ccr_status;
UINT32 ret=0;

configVbus1();

printf ("\nChecking PIO access of VBUS 1 AFE %x registers 0x80 to 0x89", afenum);
/******************************/
/* Writing V-bus1 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_write( VIF_RWDR, 0x00005a56);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_write( VIF_RWCR, 0x40000086 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

/******************************/
/* Reading V-bus1 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000086 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_read_check(VIF_RRCR, 0x00005a56);

/******************************/
/* Writing V-bus1 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_write( VIF_RWDR, 0x00005a57);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_write( VIF_RWCR, 0x40000087 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

/******************************/
/* Reading V-bus1 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000087 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));


pio_read_check(VIF_RRCR, 0x00005a57);

/******************************/
/* Writing V-bus1 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));


pio_write( VIF_RWDR, 0x00005a58);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_write( VIF_RWCR, 0x40000088 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

/******************************/
/* Reading V-bus1 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000088 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_read_check(VIF_RRCR, 0x00005a58);


/******************************/
/* Writing V-bus1 register  ..... */
/******************************/
pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_write( VIF_RWDR, 0x00005a59);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_write( VIF_RWCR, 0x40000089 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit30) !=0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

/******************************/
/* Reading V-bus1 register  ..... */
/******************************/
pio_write( VIF_RWCR, 0x80000089 + afenum);

pio_read (VIF_RASR, (&afe_vbus1_ccr_status));
while((afe_vbus1_ccr_status & _bit31) ==0 )
	pio_read (VIF_RASR, (&afe_vbus1_ccr_status));

pio_read_check(VIF_RRCR, 0x00005a59);


    ret = testVbusIFEReg(afenum);
    if (ret) {
        printf("\nIFE register test passed!\n"); 
        return OK;
    }
    else {
        fnum++;
        printf("\nIFE register test failed!\n"); 
        return ERROR;
    }

}/*end of test*/

int vbus1_test(void)
{
    return(ref_afe_vbus1_pio_rw (2<<8));
}


/* This file does PIO register read and write operation 
* date 05/20/01
*/ 

UINT32 PioRegTst(UINT32 baseAddress, UINT32 mask, UINT32 NumofCh, char *name)
{
        UINT32  ch;
        UINT32  addr;
        UINT32   data, read_back;
        int  fail_flag = 0;
        

        for (ch = 0; ch < NumofCh; ch++) {
                addr = baseAddress | (ch << 2);

                data = _32b & mask;

                pio_write(addr, data);

                read_back = pio_read_return(addr);

                if ((read_back & mask) != (data & mask)) {
#ifdef _DEBUG
                  printf( "**** PIO Read Failed\n");
                  printf( "**** Address = %lx, Actual = %lx, Expected = %lx\n", addr, read_back, data);
#endif
                  fail_flag = 1;
                  exit(0);

                } else {                 
#if 0
                  printf( "**** PIO Read of Address = %lx Passed\n", addr);
#endif
                }


                data = 0;

                pio_write(addr, data);

                read_back = pio_read_return(addr);

                if ((read_back & mask) != (data & mask)) {
#ifdef _DEBUG
                     printf( "**** PIO Read Failed\n");
                     printf( "**** Address = %lx, Actual = %lx, Expected = %lx\n", addr, read_back, data);
#endif
                     fail_flag = 1;
                     exit(0);
                }
        }

        if(fail_flag == 0)
{
#ifdef _DEBUG 
          printf("-------- PioRegTst PASSED: %s --------\n", name);
#endif
}
        else {
            failFlag = ERROR;
            printf("-------- PioRegTst FAILED: %s --------\n", name);
        }

	return (1);

}


UINT32 TNI_PioTst()
{

	printf("---- Start of the TNI test ----\n");

	PioRegTst(REG_TNI_CH_FAST_0, _7b << 25, 32, "TNI_CH_FAST"); 
	PioRegTst(REG_TNI_CH_INLV_0, _7b << 25, 32, "TNI_CH_INLV"); 

	PioRegTst(REG_TNI_PHY_LOW_0, _6b << 26, 32, "TNI_PHY_LOW"); 
#ifndef BME_CPE_20
	PioRegTst(REG_TNI_PHY_HIGH_0, _6b << 26, 32, "TNI_PHY_HIGH"); 
#endif

	PioRegTst(REG_TNI_PHY_LOW_ONOFF_0, _1b << 31, 32, "TNI_PHY_LOW_ONOFF"); 
#ifndef BME_CPE_20
	PioRegTst(REG_TNI_PHY_HIGH_ONOFF_0, _1b << 31, 32, "TNI_HIGH_ON_OFF"); 
	
    PioRegTst(TNI_CSR, _8b << 24, 1, "TNI_CELL_SIZE"); 
	PioRegTst(TNI_LOOR, _3b << 29, 1, "TNI_LEVEL_ONFO"); 
#endif
	printf( "**** End of the TNI test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }

}

UINT32 Xfifo_PioTst()
{

	printf( "**** Start of the XFIFO test\n");
#ifdef BME_CPE_20
	PioRegTst(REG_XFIFO_F_CXFT_A, 0xe007, 1, "XFIFO_F_CXFT_A"); 
	PioRegTst(REG_XFIFO_F_CXFT_B, _30b, 1, "XFIFO_F_CXFT_B"); 

	PioRegTst(REG_XFIFO_I_CXFT_A, 0xe007, 1, "XFIFO_I_CXFT_A");
	PioRegTst(REG_XFIFO_I_CXFT_B, _30b, 1, "XFIFO_I_CXFT_B"); 
#else
	PioRegTst(REG_XFIFO_F_CXFT_A, _16b, 32, "XFIFO_F_CXFT_A"); 
	PioRegTst(REG_XFIFO_F_CXFT_B, _30b, 32, "XFIFO_F_CXFT_B"); 

	PioRegTst(REG_XFIFO_I_CXFT_A, _16b, 32, "XFIFO_I_CXFT_A");
	PioRegTst(REG_XFIFO_I_CXFT_B, _30b, 32, "XFIFO_I_CXFT_B"); 
#endif
	printf( "**** End of the XFIFO test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Micro_cont_PioTst()
{

	printf( "**** Start of the Frm Microcontroller test\n");

	/* Hardware internally clears the last bit of FMC_FCR, so the mask has
	 * to be 0x06 instead of _3b (0x07) 
	 */ 
	PioRegTst(FMC_FCR, 0x06, 1, "FRM_FMC_FCR");

	printf( "**** End of the Frm Micro Controller test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Yfifo_PioTst()
{

	printf( "**** Start of the Yfifo test\n");
#ifdef BME_CPE_20
	PioRegTst(REG_YFIFO_CYFT_A, _3b, 1, "YFIFO_CYFT_A");
    PioRegTst(REG_YFIFO_CYFT_B, _32b, 1, "YFIFO_CYFT_B");

	/* 15..5 are reserved for CYFT_C */ 
	PioRegTst(REG_YFIFO_CYFT_C, _16b << 16 , 1, "YFIFO_CYFT_C");
	PioRegTst(REG_YFIFO_CYFT_C, _5b, 1, "YFIFO_CYFT_C");

	PioRegTst(REG_YFIFO_CYFT_D, _32b, 1, "YFIFO_CYFT_D");
#else
	PioRegTst(REG_YFIFO_TOFT, _YFI_TOFT_MASK, 1, "YFIFO_TOFT");
	PioRegTst(REG_YFIFO_CYFT_A, _19b, 32, "YFIFO_CYFT_A");
	
    PioRegTst(REG_YFIFO_CYFT_B, _32b, 32, "YFIFO_CYFT_B");

	/* 15..5 are reserved for CYFT_C */ 
	PioRegTst(REG_YFIFO_CYFT_C, _16b << 16 , 32, "YFIFO_CYFT_C");
	PioRegTst(REG_YFIFO_CYFT_C, _5b, 32, "YFIFO_CYFT_C");

	PioRegTst(REG_YFIFO_CYFT_D, _32b, 32, "YFIFO_CYFT_D");
#endif	
    printf( "**** End of the Yfifo test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Mapper_PioTst()
{

	printf( "**** Start of the Mapper PIO test\n");

	PioRegTst(PTONE_32T_GL, _32b, 1, "PTONE_32T");
	PioRegTst(PTONE_64T_GL, _32b, 1, "PTONE_64T");
	PioRegTst(PTONE_128T_GL, _32b, 1, "PTONE_128T");
	PioRegTst(PTONE_256T_GL, _32b, 1, "PTONE_256T");
	PioRegTst(PTONE_512T_GL, _32b, 1,  "PTONE_512T");
	PioRegTst(PTONE_1024T_GL, _32b, 1, "PTONE_1024T");
	PioRegTst(PTONE_2048T_GL, _32b, 1, "PTONE_2048T");
	
	PioRegTst(REG_MAP_MCT, _16b, 32, "MAP_ACT");

	printf( "**** End of the Mapper PIO test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}                                        

UINT32 Zfifo_PioTst()
{

	printf( "**** Start of the ZFIFO test\n");

#ifdef BME_CPE_20
	PioRegTst(REG_ZFIFO_CZFT_A, _3b, 1, "ZFIFO_CZFT_A"); 
	PioRegTst(REG_ZFIFO_CZFT_C, _18b, 1, "ZFIFO_CZFT_C");
	PioRegTst(REG_ZFIFO_CZFT_D, _18b, 1, "ZFIFO_CZFT_D");
	PioRegTst(REG_ZFIFO_PFXT_A, _ZPFXTA_MASK, 1, "ZFIFO_PFXT_A");
	PioRegTst(REG_ZFIFO_PFXT_B, _25b, 1, "ZFIFO_PFXT_B");
	PioRegTst(REG_ZFIFO_PFXT_C, _9b, 1, "ZFIFO_PFXT_C");
#else
	PioRegTst(REG_ZFIFO_CZFT_A, _20b, 32, "ZFIFO_CZFT_A"); 
	PioRegTst(REG_ZFIFO_CZFT_C, _18b, 32, "ZFIFO_CZFT_C");
	PioRegTst(REG_ZFIFO_CZFT_D, _18b, 32, "ZFIFO_CZFT_D");
	PioRegTst(REG_ZFIFO_PFXT_A, _ZPFXTA_MASK, 32, "ZFIFO_PFXT_A");
	PioRegTst(REG_ZFIFO_PFXT_B, _25b, 32, "ZFIFO_PFXT_B");
	PioRegTst(REG_ZFIFO_PFXT_C, _9b, 32, "ZFIFO_PFXT_C");
#endif


	printf( "**** End of the ZFIFO test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Vbus_CSTLOW_PioTst(vul addr, char cst[])
{
	PioRegTst(addr, _8b << 8, 1, cst);
	PioRegTst(addr, _5b, 1, cst);
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Vbus_CSTHIGH_PioTst(vul addr, char cst[])
{
	PioRegTst(addr, _32b, 1, cst);
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
	}
}

UINT32 VBus_PioTst()
{ 

	int i;
	char cstname[32];

	printf( "**** Start of the VBus test\n");


	PioRegTst(VIF_BCR, _2b << 30, 1, "Vbus_VIF_BCR");

	PioRegTst(VIF_ICCR, _10b << 16, 1, "Vbus_VIF_ICCR");
	/* bit 15:10 is reserved  */
	PioRegTst(VIF_ICCR, _10b, 1, "Vbus_VIF_ICCR");

	PioRegTst(VIF_RWCR, _VIF_RWCR_MASK, 1, "Vbus_VIF_RWCR");

	PioRegTst(VIF_RRCR, 0x0, 1, "Vbus_VIF_RRCR");

	PioRegTst(VIF_RWDR, _32b, 1, "Vbus_VIF_RWDR");

	PioRegTst(VIF_RASR, 0x0 << 27, 1, "Vbus_VIF_RASR");

	PioRegTst(VIF_SCCR, _5b << 24, 1, "Vbus_VIF_SCCR");
	PioRegTst(VIF_SCCR, _5b << 16, 1, "Vbus_VIF_SCCR");
	PioRegTst(VIF_SCCR, _4b << 8, 1, "Vbus_VIF_SCCR");
	PioRegTst(VIF_SCCR, _4b, 1, "Vbus_VIF_SCCR");

	PioRegTst(VIF_CLMR, _2b << 30, 1, "Vbus_VIF_CLMR");
	PioRegTst(VIF_TSCR, _32b, 1, "Vbus_VIF_TSCR");
	PioRegTst(VIF_RSCR, _16b, 1, "Vbus_VIF_RSCR");
	PioRegTst(VIF_RSCR, _16b, 1, "Vbus_VIF_RSCR");

	/* Channel schedule table LOW registers 0 thru 31 */ 

	for (i = 0; i < 32; i++) { 
		sprintf(cstname, "Vbus_VIF_CSTLOW #%d", i);
		Vbus_CSTLOW_PioTst(VIF_CST0L | (i * 0x08), cstname); 
	}

	/* Channel schedule table HIGH registers 0 thru 31 */ 

	for (i = 0; i < 32; i++) { 
		sprintf(cstname, "Vbus_VIF_CSTHIGH #%d", i); 
		Vbus_CSTHIGH_PioTst(VIF_CST0H | (i * 0x08), cstname); 
	}

	printf( "**** End of the VBus test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}                    


UINT32 Afifo_PioTst()
{

	printf( "**** Start of the AFIFO test\n");

#ifdef BME_CPE_20
	PioRegTst(REG_AFIFO_CAFT_A, _3b, 1, "AFIFO_CAFT_A");
	PioRegTst(REG_AFIFO_CAFT_C, _18b, 1, "AFIFO_CAFT_C");
	PioRegTst(REG_AFIFO_CAFT_D, _18b, 1, "AFIFO_CAFT_D");
#else
	PioRegTst(REG_AFIFO_CAFT_A, _20b, 32, "AFIFO_CAFT_A");
	PioRegTst(REG_AFIFO_CAFT_C, _18b, 32, "AFIFO_CAFT_C");
	PioRegTst(REG_AFIFO_CAFT_D, _18b, 32, "AFIFO_CAFT_D");
#endif
	printf( "**** End of the AFIFO test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Rcv_Micro_cont_PioTst()
{

	printf( "**** Start of the VBus test\n");
	
	/* Hardware internally clears the last bit of FMC_FCR, so the mask has
	 * to be 0x06 instead of _3b (0x07) 
	 */ 
	PioRegTst(RMC_RCR, 0x06, 1, "Rcv_micro_cont_RMC_RCR");
	
	printf( "**** End of the Rcv Micro Controller test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Feq_PioTst()
{
	return (1);
}

UINT32 Dmap_PioTst()
{

	printf( "**** Start of the Demapper test\n");

	PioRegTst(REG_DMAP_DMPCTX, _16b << 16, 32, "DMAP_DMPCTX");
	PioRegTst(REG_DMAP_DMPCTX, _7b << 8, 32, "DMAP_DMPCTX");
	PioRegTst(REG_DMAP_DMPCTX, _7b, 32, "DMAP_DMPCTX");

	PioRegTst(REG_DMAP_DMPMUT, _4b, 32, "DMAP_DMPMUT");
	PioRegTst(REG_DMAP_SNRCTX, _12b, 32, "DMAP_SNRCTX");

	printf( "**** End of the Demapper test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Bfifo_PioTst()
{
	printf( "**** Start of the BFIFO test\n");

#ifdef BME_CPE_20
	PioRegTst(REG_BFIFO_CDMT, _32b, 1, "BFIFO_CDMT");
	PioRegTst(REG_BFIFO_CBFT_B, _28b, 1, "BFIFO_CBFT_B");
	
	PioRegTst(REG_BFIFO_CBIT_A, _3b, 1, "BFIFO_CBIT_A");
	PioRegTst(REG_BFIFO_CBIT_B, _32b, 1, "BFIFO_CBIT_B");
	
	PioRegTst(REG_BFIFO_CBIT_C, _16b << 16, 1, "BFIFO_CBIT_C");
	PioRegTst(REG_BFIFO_CBIT_C, _5b, 1, "BFIFO_CBIT_C");

	PioRegTst(REG_BFIFO_CBIT_D, _16b << 16, 1, "BFIFO_CBIT_D");
#else
	PioRegTst(REG_BFIFO_CDMT, _32b, 32, "BFIFO_CDMT");
	PioRegTst(REG_BFIFO_CBFT_B, _28b, 32, "BFIFO_CBFT_B");
	
	PioRegTst(REG_BFIFO_CBIT_A, _17b, 32, "BFIFO_CBIT_A");
	PioRegTst(REG_BFIFO_CBIT_B, _32b, 32, "BFIFO_CBIT_B");
	
	PioRegTst(REG_BFIFO_CBIT_C, _16b << 16, 32, "BFIFO_CBIT_C");
	PioRegTst(REG_BFIFO_CBIT_C, _5b, 32, "BFIFO_CBIT_C");

	PioRegTst(REG_BFIFO_CBIT_D, _16b << 16, 32, "BFIFO_CBIT_D");
#endif

	printf( "**** End of the BFIFO test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}


UINT32 Dfrm_Micro_cont_PioTst()
{

	printf( "**** Start of the Deframer Micro controller test\n");

	/* Hardware internally clears the last bit of FMC_FCR, so the mask has
	 * to be 0x06 instead of _3b (0x07) 
	 */ 
	 
	PioRegTst(DMC_DCR, 0x06, 1, "DMC_DCR");

	printf( "**** End of the Deframer Micro-cont test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Cfifo_PioTst()
{

	printf( "**** Start of the Cfifo Pio test\n");

#ifndef BME_CPE_20
	PioRegTst(REG_CFIFO_CCFT0_A, _16b, 32, "CFIFO_CCFT0_A");
	PioRegTst(REG_CFIFO_CCFT1_A, _16b, 32, "CFIFO_CCFT1_A");
#else
	PioRegTst(REG_CFIFO_CCFT0_A, _3b, 32, "CFIFO_CCFT0_A");
#endif
	PioRegTst(REG_CFIFO_CCFT0_B, _30b, 32, "CFIFO_CCFT0_B");
#ifndef BME_CPE_20
	PioRegTst(REG_CFIFO_CCFT1_B, _30b, 32, "CFIFO_CCFT1_B");
#endif

	printf( "**** End of the Cfifo Pio test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 RNI_PioTst()
{

	printf( "**** Start of the RNI test\n");

	PioRegTst(RNI_MCR, _3b << 29, 1, "RNI_MCR");
	PioRegTst(RNI_MCR, _8b << 16, 1, "RNI_MCR");
	
	PioRegTst(REG_RNI_PHY_CTRL_A, _RNI_PHY_MASK << 31, 32, "RNI_PHY_CTRL_A");

	PioRegTst(REG_RNI_PHY_CTRL_B, _RNI_PHY_MASK << 31, 32, "RNI_PHY_CTRL_B");

	printf( "**** End of the RNI test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}

UINT32 Pio_Interface_PioTst()
{
 UINT32 data;


	printf( "**** Start of the Pio interface test\n");

	PioRegTst(PIO_MCR, _1b << 31, 1, "PIO_MCR");
	PioRegTst(PIO_MCR, _1b, 1, "PIO_MCR");

	PioRegTst(CKM_CCR, _11b << 16, 1, "Pio_CKM_CCR");
	PioRegTst(CKM_CCR, _13b, 1, "Pio_CKM_CCR");
#ifndef BME_CPE_20
	PioRegTst(CKM_PCR, _3b << 24, 1, "Pio_CKM_PCR");
#endif
	PioRegTst(CKM_PCR, _1b << 16, 1, "Pio_CKM_PCR");
#ifndef BME_CPE_20
	PioRegTst(CKM_PCR, _9b, 1, "Pio_CKM_PCR");
#endif

	PioRegTst(PIO_ISR, _1b << 24, 1, "Pio_PIO_ISR"); 
	PioRegTst(PIO_ISR, _1b << 16, 1, "Pio_PIO_ISR"); 
	PioRegTst(PIO_ISR, _1b, 1, "Pio_PIO_ISR"); 

	/* PioRegTst(PIO_RSR, _1b, 1, "Pio_PIO_RSR"); */
        pio_read (PIO_RSR, &data);
    /*      if(data != 0x1)
            {
            printf( "**** PIO_RSR read test failed"); 
            exit(0);
            }
      */  
            

	PioRegTst(DAC_MCR, _16b, 1, "Pio_PIO_RSR");

	printf( "**** End of the Pio test\n");
    if (failFlag == OK) 
        return (OK);	
    else{
        fnum++;
        return (ERROR);	
    }
}


UINT32 ref_host_pio_rd_wr (int argc, char * argv[])
{

        TNI_PioTst();
        Xfifo_PioTst();
        Micro_cont_PioTst();
        Yfifo_PioTst();
        Mapper_PioTst();
        Zfifo_PioTst();
        VBus_PioTst();
        Afifo_PioTst();
        Rcv_Micro_cont_PioTst();
        Dmap_PioTst();
        Bfifo_PioTst();
        Dfrm_Micro_cont_PioTst();
        Cfifo_PioTst();
        RNI_PioTst();
        Pio_Interface_PioTst();
	return (1);
}

/*To clear download errors. These funcions are not used */
void BmeMemoryRead(){}
void BmeMemoryWrite(){}
void BinSettings(){}
